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Semiconductor device fabrication |
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MOSFET scaling (process nodes) |
Future
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Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips (such as NAND flash and DRAM). It is a multiple-step photolithographic and physico-chemical process (with steps such as thermal oxidation, thin-film deposition, ion-implantation, etching) during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.
The fabrication process is performed in highly specialized semiconductor fabrication plants, also called foundries or "fabs",[1] with the central part being the "clean room". In more advanced semiconductor devices, such as modern 14/10/7 nm nodes, fabrication can take up to 15 weeks, with 11–13 weeks being the industry average.[2] Production in advanced fabrication facilities is completely automated, with automated material handling systems taking care of the transport of wafers from machine to machine.[3]
A wafer often has several integrated circuits which are called dies as they are pieces diced from a single wafer. Individual dies are separated from a finished wafer in a process called die singulation, also called wafer dicing. The dies can then undergo further assembly and packaging.[4]
Within fabrication plants, the wafers are transported inside special sealed plastic boxes called FOUPs.[3] FOUPs in many fabs contain an internal nitrogen atmosphere[5][6] which helps prevent copper from oxidizing on the wafers. Copper is used in modern semiconductors for wiring.[7] The insides of the processing equipment and FOUPs is kept cleaner than the surrounding air in the cleanroom. This internal atmosphere is known as a mini-environment and helps improve yield which is the amount of working devices on a wafer. This mini environment is within an EFEM (equipment front end module)[8] which allows a machine to receive FOUPs, and introduces wafers from the FOUPs into the machine. Additionally many machines also handle wafers in clean nitrogen or vacuum environments to reduce contamination and improve process control.[3] Fabrication plants need large amounts of liquid nitrogen to maintain the atmosphere inside production machinery and FOUPs, which are constantly purged with nitrogen.[5][6] There can also be an air curtain or a mesh[9] between the FOUP and the EFEM which helps reduce the amount of humidity that enters the FOUP and improves yield.[10][11]
Companies that manufacture machines used in the industrial semiconductor fabrication process include ASML, Applied Materials, Tokyo Electron and Lam Research.
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Transcription
Feature size
Feature size is determined by the width of the smallest lines that can be patterned in a semiconductor fabrication process, this measurement is known as the linewidth.[12][13] Patterning often refers to photolithography which allows a device design or pattern to be defined on the device during fabrication.[14] F2 is used as a measurement of area for different parts of a semiconductor device, based on the feature size of a semiconductor manufacturing process. Many semiconductor devices are designed in sections called cells, and each cell represents a small part of the device such as a memory cell to store data. Thus F2 is used to measure the area taken up by these cells or sections.[15]
A specific semiconductor process has specific rules on the minimum size (width or CD/Critical Dimension) and spacing for features on each layer of the chip.[16] Normally a new semiconductor process has smaller minimum sizes and tighter spacing. In some cases, this allows a simple die shrink of a currently produced chip design to reduce costs, improve performance,[16] and increase transistor density (number of transistors per unit area) without the expense of a new design.
Early semiconductor processes had arbitrary names for generations (viz., HMOS I/II/III/IV and CHMOS III/III-E/IV/V). Later each new generation process became known as a technology node[17] or process node,[18][19] designated by the process' minimum feature size in nanometers (or historically micrometers) of the process's transistor gate length, such as the "90 nm process". However, this has not been the case since 1994,[20] and the number of nanometers used to name process nodes (see the International Technology Roadmap for Semiconductors) has become more of a marketing term that has no standardized relation with functional feature sizes or with transistor density (number of transistors per unit area).[21]
Initially transistor gate length was smaller than that suggested by the process node name (e.g. 350 nm node); however this trend reversed in 2009.[20] Feature sizes can have no connection to the nanometers (nm) used in marketing. For example, Intel's former 10 nm process actually has features (the tips of FinFET fins) with a width of 7 nm, so the Intel 10 nm process is similar in transistor density to TSMC's 7 nm process. As another example, GlobalFoundries' 12 and 14 nm processes have similar feature sizes.[22][23][21]
History
20th century
An improved type of MOSFET technology, CMOS, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963.[24][25] CMOS was commercialised by RCA in the late 1960s.[24] RCA commercially used CMOS for its 4000-series integrated circuits in 1968, starting with a 20 μm process before gradually scaling to a 10 μm process over the next several years.[26] Many early semiconductor device manufacturers developed and built their own equipment such as ion implanters.[27]
In 1963, Harold M. Manasevit was the first to document epitaxial growth of silicon on sapphire while working at the Autonetics division of North American Aviation (now Boeing). In 1964, he published his findings with colleague William Simpson in the Journal of Applied Physics.[28] In 1965, C.W. Mueller and P.H. Robinson fabricated a MOSFET (metal–oxide–semiconductor field-effect transistor) using the silicon-on-sapphire process at RCA Laboratories.[29]
Semiconductor device manufacturing has since spread from Texas and California in the 1960s to the rest of the world, including Asia, Europe, and the Middle East.
Wafer size has grown over time, from 25 mm in 1960, to 50 mm in 1969, 100 mm in 1976, 125 mm in 1981, 150 mm in 1983 and 200 mm in 1992.[30][31]
In the era of 2 inch wafers, these were handled manually using tweezers and held manually for the time required for a given process. Tweezers were replaced by vacuum wands as they generate fewer particles[32] which can contaminate the wafers. Wafer carriers or cassettes, which can hold several wafers at once, were developed to carry several wafers between process steps, but wafers had to be individually removed from the carrier, processed and returned to the carrier, so acid-resistant carriers were developed to eliminate this time consuming process, so the entire cassette with wafers was dipped into wet etching and wet cleaning tanks. When wafer sizes increased to 100 mm, the entire cassette would often not be dipped as uniformly, and the quality of the results across the wafer, became hard to control. By the time 150 mm wafers arrived, the cassettes were not dipped and were only used as wafer carriers and holders to store wafers, and robotics became prevalent for handling wafers. With 200 mm wafers manual handling of wafer cassettes becomes risky as they are heavier.[33]
In the 1970s, several companies migrated their semiconductor manufacturing technology from bipolar to CMOS technology.[34] Semiconductor manufacturing equipment has been considered costly since 1978.[35]
In 1984, KLA developed the first automatic reticle and photomask inspection tool.[36] In 1985, KLA developed an automatic inspection tool for silicon wafers, which replaced manual microscope inspection.[37]
In 1985, STmicroelectronics invented BCD, also called BCDMOS, a semiconductor manufacturing process using Bipolar, CMOS and LDMOS devices.[38] It can also be made with Bipolar, CMOS and DMOS devices.[39] Applied Materials developed the first practical multi chamber, or cluster wafer processing tool, the Precision 5000.[40]
Until the 1980s, physical vapor deposition was the primary technique used for depositing materials onto wafers, until the advent of chemical vapor deposition.[41] Equipment with diffusion pumps was replaced with those using turbomolecular pumps as the latter do not use oil which often contaminated wafers during processing in vacuum.[42]
200 mm diameter wafers were first used in 1990 for making chips. These became the standard until the introduction of 300 mm diameter wafers in 2000.[43][44] Bridge tools were used in the transition from 150 mm wafers to 200 mm wafers[45] and in the transition from 200 mm to 300 mm wafers.[46][47] The semiconductor industry has adopted larger wafers to cope with the increased demand for chips as larger wafers provide more surface area per wafer.[48] Over time, the industry shifted to 300 mm wafers which brought along the adoption of FOUPs,[49] but many products that are not advanced are still produced in 200 mm wafers such as analog ICs, RF chips, power ICs, BCDMOS and MEMS devices.[50] Some processes such as cleaning,[51] ion implantation,[52][53] etching,[54] annealing[55] and oxidation[56] started to adopt single wafer processing instead of batch wafer processing in order to improve the reproducibility of results.[57][58] A similar trend existed in MEMS manufacturing.[59] In 1998, Applied Materials introduced the Producer, a cluster tool that had chambers grouped in pairs for processing wafers, which shared common vacuum and supply lines but were otherwise isolated, which was revolutionary at the time as it offered higher productivity than other cluster tools without sacrificing quality, due to the isolated chamber design.[60][45]
21st century
The semiconductor industry is a global business today. The leading semiconductor manufacturers typically have facilities all over the world. Samsung Electronics, the world's largest manufacturer of semiconductors, has facilities in South Korea and the US. Intel, the second-largest manufacturer, has facilities in Europe and Asia as well as the US. TSMC, the world's largest pure play foundry, has facilities in Taiwan, China, Singapore, and the US. Qualcomm and Broadcom are among the biggest fabless semiconductor companies, outsourcing their production to companies like TSMC.[61] They also have facilities spread in different countries. As the average utilization of semiconductor devices increased, durability became an issue and manufacturers started to design their devices to ensure they last for enough time, and this depends on the market the device is designed for. This especially became a problem at the 10 nm node.[62][63]
Silicon on insulator (SOI) technology has been used in AMD's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors made since 2001.[64] During the transition from 200 mm to 300 mm wafers in 2001, many bridge tools were used which could process both 200 mm and 300 mm wafers.[65] At the time, 18 companies could manufacture chips in the leading edge 130nm process.[66]
In 2006, 450 mm wafers were expected to be adopted in 2012, and 675 mm wafers were expected to be used by 2021.[67]
Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.[68][69][70] For example, GlobalFoundries' 7 nm process was similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred.[71] Additionally, TSMC and Samsung's 10 nm processes are only slightly denser than Intel's 14 nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the exact same as that of Intel's 14 nm process: 42 nm).[72][73] Intel has changed the name of its 10 nm process to position it as a 7 nm process.[74] As transistors become smaller, new effects start to influence design decisions such as self-heating of the transistors, and other effects such as electromigration have become more evident since the 16nm node.[75][76]
In 2011, Intel demonstrated Fin field-effect transistors (FinFETs), where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors at the 22nm node, because planar transistors which only have one surface acting as a channel, started to suffer from short channel effects.[77][78][79][80][81] A startup called SuVolta created a technology called Deeply Depleted Channel (DDC) to compete with FinFET transistors, which uses planar transistors at the 65 nm node which are very lightly doped.[82]
By 2018, a number of transistor architectures had been proposed for the eventual replacement of FinFET, most of which were based on the concept of GAAFET:[83] horizontal and vertical nanowires, horizontal nanosheet transistors[84][85] (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors,[86][87] complementary FET (CFET), stacked FET, vertical TFETs, FinFETs with III-V semiconductor materials (III-V FinFET),[88][89] several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors[90] and negative-capacitance FET (NC-FET) which uses drastically different materials.[91] FD-SOI was seen as a potential low cost alternative to FinFETs.[92]
As of 2019, 14 nanometer and 10 nanometer chips are in mass production by Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory and GlobalFoundries, with 7 nanometer process chips in mass production by TSMC and Samsung, although their 7 nanometer node definition is similar to Intel's 10 nanometer process. The 5 nanometer process began being produced by Samsung in 2018.[93] As of 2019, the node with the highest transistor density is TSMC's 5 nanometer N5 node,[94] with a density of 171.3 million transistors per square millimeter.[95] In 2019, Samsung and TSMC announced plans to produce 3 nanometer nodes. GlobalFoundries has decided to stop the development of new nodes beyond 12 nanometers in order to save resources, as it has determined that setting up a new fab to handle sub-12 nm orders would be beyond the company's financial abilities.[96]
From 2020 to 2022, there was a global chip shortage. During this shortage caused by the COVID-19 pandemic, many semiconductor manufacturers banned employees from leaving company grounds.[97] Many countries grant subsidies to semiconductor companies for building new fabrication plants or fabs. Many companies were affected by counterfeit chips.[98] Semiconductors have become vital to the world economy and the national security of some countries.[99][100][101] The US has asked TSMC to not produce semiconductors for Huawei, a Chinese company.[102] CFET transistors were explored, which stacks NMOS and PMOS transistors on top of each other. Two approaches were evaluated for constructing these transistors: a monolithic approach which built both types of transistors in one process, and a sequential approach which built the two types of transistors separately and then stacked them.[103]
List of steps
This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order, nor that all techniques are taken during manufacture as, in practice the order and which techniques are applied, are often specific to process offerings by foundries, or specific to an integrated device manufacturer (IDM) for their own products, and a semiconductor device might not need all techniques. Equipment for carrying out these processes is made by a handful of companies. All equipment needs to be tested before a semiconductor fabrication plant is started.[104] These processes are done after integrated circuit design. A semiconductor fab operates 24/7[105] and many fabs use large amounts of water, primarily for rinsing the chips.[106]
- Wafer processing (also called front end)[107]
- Wet cleans
- Cleaning by solvents such as acetone, trichloroethylene or ultrapure water sometimes while spinning the wafer
- Piranha solution
- RCA clean
- Wafer scrubbing
- Spin cleaning[108]
- Jet spray cleaning[108]
- Cryogenic aerosol[109]
- Megasonics[110]
- Immersion batch cleaning[111]
- Surface passivation
- Photolithography
- Photoresist coating (often as a liquid, on the entire wafer)
- Photoresist baking (solidification in an oven)
- Edge bead removal[112][113]
- Exposure (in a photolithography stepper, scanner or mask aligner)
- Post Exposure Baking (PEB) improves the durability of the photoresist
- Development (removal of parts of the resist by application of a liquid developer, leaving only parts of the wafer exposed for ion implantation, layer deposition, etching, etc)
- Ion implantation (in which dopants are embedded in the wafer creating regions of increased or decreased conductivity)
- Etching (microfabrication)
- Dry etching (plasma etching)
- Reactive-ion etching (RIE)
- Deep reactive-ion etching (DRIE)
- Atomic layer etching (ALE)
- Reactive-ion etching (RIE)
- Wet etching
- Dry etching (plasma etching)
- Chemical vapor deposition (CVD)
- Metal organic chemical vapor deposition (MOCVD), used in LEDs
- Atomic layer deposition (ALD)
- Physical vapor deposition (PVD)
- Sputtering
- Evaporation
- Epitaxy[103][115]
- Ion beam deposition[117]
- Plasma ashing (for complete photoresist removal/photoresist stripping, also known as dry strip,[118] historically done with a chemical solvent called a resist stripper,[119] [120] to allow wafers to undergo another round of photolithography)
- Thermal treatments
- Rapid thermal processing (RTP), rapid thermal anneal
- Millisecond thermal processing, millisecond anneal, millisecond processing, flash lamp anneal (FLA)
- Laser anneal
- Furnace anneals
- Thermal oxidation
- Laser lift-off (for LED production[121])
- Electrochemical deposition (ECD). See Electroplating.
- Chemical-mechanical polishing (CMP)
- Wafer testing (where the electrical performance is verified using automatic test equipment, binning and/or laser trimming may also be carried out at this step)
- Wet cleans
- Die preparation
- Through-silicon via manufacture (for three-dimensional integrated circuits)
- Wafer mounting (wafer is mounted onto a metal frame using dicing tape)
- Wafer backgrinding and polishing[122] (reduces the thickness of the wafer for thin devices like a smartcard or PCMCIA card or wafer bonding and stacking, this can also occur during wafer dicing, in a process known as Dice Before Grind or DBG[123][124])
- Wafer bonding and stacking (for three-dimensional integrated circuits and MEMS)
- Redistribution layer manufacture (for WLCSP packages)
- Wafer bumping (for flip chip BGA (ball grid array), and WLCSP packages)
- Die cutting or wafer dicing
- IC packaging
- Die attachment (The die is attached to a leadframe using conductive paste or die attach film.[125][126])
- IC bonding: Wire bonding, thermosonic bonding, flip chip or tape automated bonding (TAB)
- IC encapsulation or integrated heat spreader (IHS) installation
- Molding (using special plastic molding compound that may contain glass powder as filler to control thermal expansion)
- Baking
- Electroplating (plates the copper leads of the lead frames with tin to make soldering easier)
- Laser marking or silkscreen printing
- Trim and form (separates the lead frames from each other, and bends the lead frame's pins so that they can be mounted on a printed circuit board)
- IC testing
Additionally steps such as Wright etch may be carried out.
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Prevention of contamination and defects
When feature widths were far greater than about 10 micrometres, semiconductor purity was not as big of an issue as it is today in device manufacturing. In the 1960s, workers could work on semiconductor devices in street clothing.[127] As devices become more integrated, cleanrooms must become even cleaner. Today, fabrication plants are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The ceilings of semiconductor cleanrooms have fan filter units (FFUs) at regular intervals to constantly replace and filter the air in the cleanroom; semiconductor capital equipment may also have their own FFUs to clean air in the equipment's EFEM which allows the equipment to receive wafers in FOUPs. The FFUs, combined with raised floors with grills, help ensure a laminar air flow, to ensure that particles are immediately brought down to the floor and do not stay suspended in the air due to turbulence. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from contamination by humans.[128] To increase yield, FOUPs and semiconductor capital equipment may have a mini environment with ISO class 1 level of dust, and FOUPs can have an even cleaner micro environment.[11][8] FOUPs and SMIF pods isolate the wafers from the air in the cleanroom, increasing yield because they reduce the number of defects caused by dust particles. Also, fabs have as few people as possible in the cleanroom to make maintaining the cleanroom environment easier, since people, even when wearing cleanroom suits, shed large amounts of particles, especially when walking.[129][128][130]