nexys4ddr
Here are 35 public repositories matching this topic...
Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.
-
Updated
Dec 5, 2019 - VHDL
Game of Balance is an accelerometer based maze navigation game, with added features of score and life, that is built on Nexys 4 DDR development board.
-
Updated
Jan 27, 2018 - VHDL
Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs
-
Updated
Aug 30, 2017 - VHDL
An audio project with the NEXYS 4 ddr
-
Updated
Apr 17, 2022 - VHDL
My experiments with Nexys4 DDR Artix-7 FPGA Board
-
Updated
Oct 1, 2020 - Verilog
FPGA based SD card reads and displays pictures and performs digital recognition experiments.
-
Updated
Sep 27, 2021 - Verilog
A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board
-
Updated
Dec 9, 2018 - Verilog
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
-
Updated
Apr 5, 2022 - VHDL
It is my Final Degree Project of Grado de TecnologĂas y Servicios de TelecomunicaciĂłn in Universidad PolitĂ©cnica de Madrid
-
Updated
Jan 24, 2019 - VHDL
An FPGA implementation of Cummings' Asynchronous FIFO
-
Updated
Apr 14, 2022 - SystemVerilog
VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.
-
Updated
Feb 23, 2021 - VHDL
Using the FPGA board Nexys Artix-7 to design a breakout game with vhdl language.
-
Updated
May 27, 2019 - VHDL
CECS 490A/490B Course; Senior Project Design
-
Updated
Jul 14, 2021 - Verilog
Improve this page
Add a description, image, and links to the nexys4ddr topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the nexys4ddr topic, visit your repo's landing page and select "manage topics."