Huda Nasih

Pipelining is a technique of decomposing a sequential process into suboperations, with each subprocess being executed in a special dedicated segment that operates concurrently with all other segments.  The overlapping of computation is made possible by associating a register with each segment in the pipeline.  The registers provide isolation between each segment so that each can operate on distinct data simultaneously.  Perhaps the simplest way of viewing the pipeline structure is to imagine that each segment consists of an input register followed by a combinational circuit. o The register holds the data. o The combinational circuit performs the suboperation in the particular segment.  A clock is applied to all registers after enough time has elapsed to perform all segment activity.  The pipeline organization will be demonstrated by means of a simple example. o To perform the combined multiply and add operations with a stream of numbers A i * B i + C i for i = 1, 2, 3, …, 7  Each suboperation is to be implemented in a segment within a pipeline. R1  A i , R2  B i Input A i and B i R3  R1 * R2, R4  C i Multiply and input C i R5  R3 + R4 Add C i to product  Each segment has one or two registers and a combinational circuit as shown in Fig. 9-2.  The five registers are loaded with new data every clock pulse. The effect of each clock is shown in Table 4-1.

The part of the computer that performs the bulk of data processing operations is called the Central Processing Unit (CPU) and is the central component of a digital computer. Its purpose is to interpret instruction cycles received from memory and perform arithmetic, logic and control operations with data stored in internal register, memory words and I/O interface units. A CPU is usually divided into two parts namely processor unit (Register Unit and Arithmetic Logic Unit) and control unit. Fig: Components of CPU Processor Unit: The processor unit consists of arithmetic unit, logic unit, a number of registers and internal buses that provides data path for transfer of information between register and arithmetic logic unit. The block diagram of processor unit is shown in figure below where all registers are connected through common buses. The registers communicate each other not only for direct data transfer but also while performing various micro-operations. Here two sets of multiplexers select register which perform input data for ALU. A decoder selects destination register by enabling its load input. The function select in ALU determines the particular operation that to be performed. For an example to perform the operation: R 3  R 1 + R 2 1. MUX A selector (SELA): to place the content of R 1 into bus A. 2. MUX B selector (SELB): to place the content of R 2 into bus B. 3. ALU operation selector (OPR): to provide arithmetic addition A + B. 4. Decoder destination selector (SELD): to transfer the content of the output bus into R 3 .