Adder

This paper presents a concurrent error detection(CED) technique for a bit-slice of a full-adder. The proposed method involves computing the sum and carry bits in two alternative ways so that transient faults will be detected by comparing the results (Sum and Carry out) obtained from the two computing paths. This technique attempts to reduce the amount of extra hardware and cost of the circuit. In order to avoid the problem of extra time we will propagate the result when the first computation is finished so that dependent computation can commence execution as soon as possible. To prove the efficiency of the proposed method, the circuit is simulated in standard CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. The proposed design involves 12.12% saving in transistor count compared to DMR (Dual Modular Redundancy) style design.

In this paper, we have designed the detailed logical circuits of 1-bit full adder- subtractor
working on analog inputs while manipulating it through half-adder, NAND, AND and OR gates integrating with ANN and Machine Learning algorithm where fixed bias is also applied with each of the designed logical gate combinations. Because hardware implementation is far better than the software manipulation so combination of designed circuit can be used to further design ANN based 4-bit or 8-bit full Adder Subtractor. Creating the new hardware device following the same circuits and techniques can reflect the best performance of Adder Subtractor over analog inputs. Resultant waveform of designed ANN based 1-bit full Adder-Subtractor and its subcircuits are completely in favor of its new hardware implementation.

Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In ...

Awal dari penggunaan penguat operasional adalah tahun 1940-an, ketika sirkuit elektronika dasar dibuat dengan menggunakan tabung vakum untuk melakukan operasi matematika seperti penjumlahan, pengurangan perkalian dan pembagian integral dan turunan Istilah penguat operasional itu sendiri baru digunakan pertama kali oleh John Ragazzini dan kawan-kawan dalam sebuah karya tulis yang dipublikasikan pada tahun 1947. Dengan cepatnya perkembangan teknologi yang saat ini merupakan hal yang sangat berpengaruh baik dalam dunia sains, teknologi bahkan bisa masuk keranah ekonomi yang sangat pesat maka sekiranya kita perlu memahami tentang apa nama komponen yang digunakan dalam sebuah rangkaian elektronikaa dan bagaimana sistem aplikasi kerja dari alat tersebut untuk memahaminya perlu diadaka praktikum dengan baik agar dapat memahami dan membandingkan sebuah rangkaian hardware dengan simulasi. Tujuan 1) Mengerti dan memahami rangkaian adder dan subtractor 2) Mampu menganalisis cara kerja rangkaian adder dan subtractor Dasar Teori Penguat operasional (Op-amp = operasional amplifier) merupakan jenis penguat elektronika swngan sambatan (coupling) arus yang memiliki bati (faktor penguat) sangat besar dengan dua masukan dan satu keluaran, pada umumnya oenguat operasional tersedia dalam bentuk sirkuit terpadu dan yang paling banyak

Abstract: We find the applications of complex numbers in almost all fields of modern science and engineering. Due to its much application a lot of research work is underway to reduce the computation requirements for the Complex binary numbers. Recent research indicates ...

Awal dari penggunaan penguat operasional adalah tahun 1940-an, ketika sirkuit elektronika dasar dibuat dengan menggunakan tabung vakum untuk melakukan operasi matematika seperti penjumlahan, pengurangan perkalian dan pembagian integral dan turunan Istilah penguat operasional itu sendiri baru digunakan pertama kali oleh John Ragazzini dan kawan-kawan dalam sebuah karya tulis yang dipublikasikan pada tahun 1947. Dengan cepatnya perkembangan teknologi yang saat ini merupakan hal yang sangat berpengaruh baik dalam dunia sains, teknologi bahkan bisa masuk keranah ekonomi yang sangat pesat maka sekiranya kita perlu memahami tentang apa nama komponen yang digunakan dalam sebuah rangkaian elektronikaa dan bagaimana sistem aplikasi kerja dari alat tersebut untuk memahaminya perlu diadaka praktikum dengan baik agar dapat memahami dan membandingkan sebuah rangkaian hardware dengan simulasi. Tujuan 1) Mengerti dan memahami rangkaian adder dan subtractor 2) Mampu menganalisis cara kerja rangkaian adder dan subtractor Dasar Teori Penguat operasional (Op-amp = operasional amplifier) merupakan jenis penguat elektronika swngan sambatan (coupling) arus yang memiliki bati (faktor penguat) sangat besar dengan dua masukan dan satu keluaran, pada umumnya oenguat operasional tersedia dalam bentuk sirkuit terpadu dan yang paling banyak

This paper presents the design and implementation of radix-8 booth Multiplier .The number of partial
products are reduced to n/2 in radix-4We can reduce the number of partial products even further to n/3 by
using a higher radix-8 in the multiplier encoding, thereby obtaining a simpler CSA tree .This implies less
delay and a smaller area size .Since this multiplication operation is for both signed and unsigned
numbers,cost of the system can also be reduced. The carry save adder (CSA) tree and the final adder can
speed up the operation of multiplier. Koggestone adder is a parallel prefix form carry look ahead adder
.We determine that by replacing carry save adder(CSA) and final two operand parallel prefix adder with
parallel prefix adders of koggestone algorithm reduces delay furthur more resulting in substantial increase
in speed of circuits.

The Common Viper has seen quite a few problems in the peripheral areas of its distribution within the North-Central and South-Veluwe. The overall numbers of it’s former distribution compared with the 1990’s situation have declined seriously .Problems like heavy disturbances ,droughts ,fragmented areas and severe damage done by forest works are a serious threat to this vulnerable species . Fieldwork done by  Anura workgroup since 2000,now is the next step to conserve and protect the last strongholds of the common Adder on the edges on the Veluwe nature reserve .

This paper presents an enhanced  32-bit carry lookahead(CLA) adder implementing using the constant delay (CD)
logic, targeting at full-custom high-speed applications. The CD
characteristic of this logic style regardless of the logic type
makes it suitable in implementing complicated logic
expressions such as addition. CD logic exhibits a unique
characteristic where the output is pre-evaluated before the
inputs from the  preceding stage is ready. This feature offers
performance advantage over static and dynamic domino logic
styles in a single-cycle multistage circuit block. Several design
considerations including timing window width adjustment and
clock distribution are discussed. Using 65-nm general-purpose
CMOS technology, the proposed logic demonstrates an average
speed up of 94% and 56% over static and dynamic domino
logic, respectively, in five different logic gates. Simulation
results of 8-bit ripple carry adders show that  CD  logic  is  39% 
and  23%  faster  than  the  static  and dynamic-based adders,
respectively. CD logic also demonstrates  39% speedup  and 
64%(22%) energy-delay product (EDP) reduction  from  static 
logic  at  100%  (10%)  data  activity in 32-bit carry look ahead
adders. For 8-bit Wallace tree multiplier, CD logic achieves a
similar speedup with at least 50% EDP reduction across all data
activities.

In this paper, interesting full adder circuits are reviewed and compared concerning speed, power consumption, and silicon area. A modified full adder is also investigated by combining hybrid logics, namely, pass transistor logic and branch based logic. This architecture uses two independent parts to generate SUM and carry signals. The results show that ultra low power evolution, very small propagation delay and small silicon area have been accomplished by this design comparing with conventional static CMOS full adder circuit. Moreover, implementation of this design into multi-bit adder provides the advantage of eliminating the need for extra inverters, saves much more silicon area, and has ultra small total power dissipation. The investigations have been made using 0.13um CMOS process.

Now a days each and every electronic gadget is designing smartly and provides number of applications, so these designs dissipate high amount of power. Reversible logic is becoming one of the best emerging design technologies having its applications in low power CMOS, Quantum computing and Nanotechnology. Reversible logic plays an important role in the design of energy efficient circuits. Adders and subtractors are the essential blocks of the computing systems. In this paper, reversible gates and circuits are designed and implemented in CMOS and pass transistor logic using Mentor graphics backend tools. A four bit ripple carry adder/subtractor and an eight-bit reversible Carry Skip Adder are implemented and compared with the conventional circuits.

Full Adder are important component in application such as Digital Signal Processing (DSP) architecture and microprocessor. In addition to its main task , which adding two numbers. This Paper presents the design of high performance low dynamic power arithmetic circuit using a new CMOS Dynamic Feedthrough Logic (DFTL) and Analyzes power and Performance of Them and Compare this to Standard CMOS Logic. This is implemented in .350um Technology. Low power DFTL Arithmetic circuits provide for smaller propagation time Delay, low energy consumption, and similar combined Delay, power consumption when compared with the standard CMOS Logic.

Power, speed and area are prime design constraints for portable electronics devices and signal processing applications. Multiplier plays an important role in DSP applications. In this paper, a low power and high speed multiplier with improved column bypassing scheme is presented. Primary power reduction is obtained by disabling the supply voltage of non-functional blocks when the operands of the multiplicands are zero. Power reduction is achieved by both architecture and circuit level modifications. The proposed multiplier consists of new adder architecture which is also responsible for reducing the power consumption and propagation delay. Simulation results are obtained with UMC 90nm and 0.9 V CMOS technology with cadence spectre simulation tool. The proposed multiplier has been compared with popular multipliers and performance parameters in terms of power dissipation, speed and area occupation are found better. The proposed multiplier is definitely a better choice for low frequency (≤ 50 MHz) applications. The results are obtained for randomly generated input test patterns having uniform distribution probability and more power can be saved if operands have more 0's than 1's.

A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent-Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed.

This paper presents a reconfigurable hardware architecture for Public-key cryptosystems. By changing the connections of coarse grain Carry-Save Adders (CSAs), the datapath provides a high perfor- mance for both RSA and Elliptic Curve Cryptography (ECC). In addi- tion, we introduce another reconfigurability for the flip-flops in order to make the best of hardware resources. The results of FPGA implemen- tation

Abstract: The pipelined accumulator forms the basic building block of arithmetic modules for DSP applications. The basic building block of an accumulator unit is the adder cell and data storage registers e.g. Flip-Flop (FF). The operational speed of FF determines the correctness and accuracy of the functionality of 12BDA. The high-speed full adders that use low power consumption is a fundamental arithmetic operation that can never be neglected in accumulator unit, and it is one of the speed-limiting elements. The efficiency of the accumulator unit is determined by the adder cell taken in to account.In this paper, a 12-Bit pipelined accumulator cell optimized for low power and high speed operation are proposed. Update rates of 150MHz are achieved by careful choice of architecture. The static, D-type flip flops used in the pipeline architecture are the dominant source of power dissipation. Hence the refresh-every-cycle operation of accumulators is exploited by using dynamic delay elem...

The addition of two binary numbers is the most fundamental and widely used
arithmetic operation. This operation is used in microprocessors, digital signal
processors, data processing application specific integrated circuits and many more.
ETA (Error Tolerant Adder) is an efficient adder which speeds up binary addition.
There is a huge improvement in the power and speed when we use an ETA. For
increasing the speed and decreasing the power dissipation, we use the logic that in an
adder circuit the delay appears mainly because of the carry propagation and also
there is a lot of power dissipation. Design of ETA is done using backend tool under
real time simulation conditions and then compares the performance of the ETA in
terms of accuracy, delay and power consumption with that of conventional adders.
The proposed architecture is then implemented using FPGA.

Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool. Cell-based design techniques, such as standard-cells and FPGAs, together with versatile hardware synthesis are rudiments for a high productivity in ASIC design. In the majority of digital signal processing (DSP) applications the critical operations are the addition, multiplication and accumulation. Addition is an indispensable operation for any digital system, DSP or control system. Therefore a fast and accurate operation of a digital system is greatly influenced by the performance of the resident adders. Adders are also very significant component in digital systems because of their widespread use in other basic digital operations such as subtraction, multiplication and division. Hence, improving performance of the digital adder would extensively advance the execution of binary operations inside a circuit compromised of such blocks. Many different adder architectures for speeding up binary addition have been studied and proposed over the last decades. For cell-based design techniques they can be well characterized with respect to circuit area and speed as well as suitability for logic optimization and synthesis. Ripple Carry Adder (RCA)[1][2] is the simplest, but slowest adders with O(n) area and O(n) delay, where n is the operand size in bits. Carry Look-Ahead (CLA)[3][4] have O(n·log(n)) area and O(log(n)) delay, but typically suffer from irregular layout. On the other hand, Carry

The addition of two binary numbers is the most fundamental and widely used
arithmetic operation. This operation is used in microprocessors, digital signal
processors, data processing application specific integrated circuits and many more.
ETA (Error Tolerant Adder) is an efficient adder which speeds up binary addition.
There is a huge improvement in the power and speed when we use an ETA. For
increasing the speed and decreasing the power dissipation, we use the logic that in an
adder circuit the delay appears mainly because of the carry propagation and also
there is a lot of power dissipation. Design of ETA is done using backend tool under
real time simulation conditions and then compares the performance of the ETA in
terms of accuracy, delay and power consumption with that of conventional adders.
The proposed architecture is then implemented using FPGA.

An adder is a digital circuit that performs addition of numbers. In many computers and other kinds of processors adders are used in the arithmetic logic units or ALU. They are also used in other parts of the processor, where they are used to calculate addresses, table indices, increment and decrement operators and similar operations.

r-way partitioning is an NP-hard problem. In this paper we present a few heuristics for clustering, which are motivated by the theory of sub/supermodular functions. The implementation based on this heuristic justifies some already published results about the approximability of the optimal solutions to this NP-hard problem using the ideas from the theory of sub/supermodular-functions. We also suggest a hypergraph model which is more natural and more suitable for modeling this problem. We give some experimental results which indicate that our methods hold promise. Our experimental results are comparable, and in some cases better than the best to date spectral partitioning methods on the standard benchmark circuits. Finally we suggest some multilevel strategies for partitioning, where in each level we employ a supermodular function based strategy which gives a suboptimal partitioning on the fused supergraph

Abstract Since all optical computation and arithmetic can be achieved by complex and complicated all optical systems, the characteristic of cascading is an essential issue indesigned schemes of all optical simple gates or circuits. Hence, the aim of this paper is designing the fan out able half adder circuit by using optical nonlinear directional couplers. There are two GaAs/SiO 2 based half adder which one of them has only carry fan out and second scheme has the ability of driving next stages for both carry and sum outputs. These approaches are simple, compact and power efficient which has the potential to be used for all optical on chip computations. BER and quality factor have been investigated which show satisfactory performance of the proposed all optical half adder.

An integration architecture for optical computing can be based on the topology of an idealized nonlinear interface. Solid state multiplexing is possible with thin film multilayer stacks resulting in polarizers and phase retarders matched to the interface. Recent progress in controlling switching behavior at a nonlinear interface and the simple integration technique may warrant increased interest in this approach to optical computing.

In recent years, processor cores for biomedical signal processing play a vital role for portable devices. The processing unit in the device performs acquisition, feature detection and decision making. The computing algorithm comprises of adders, multipliers, registers, and buffers. Adders are the basic building blocks of multipliers, filters and feature extraction units. Discrete Wavelet transform is one of the important methods used to filter and extract information from biomedical signals which can be one dimensional or multidimensional. Fault avoidance and tolerance have been approached in past for achieving efficient and reliable system. These prevention and tolerance through redundancy can avoid failures. Different redundancies are adopted through information processing, hardware, software and time redundancy. Fault tolerant circuits can improve the efficiency of the biomedical system like DWT cores. The main objective is to design a reconfigurable full adder with self-checking and self-repairing faults for the DWT architecture. This paper presents a proposed FPGA based fault detection and repairing circuit including the fault location. The existing method uses an on-chip based adder which is complex and is less efficient and not suitable for reprogramming. In the proposed design, DWT architecture was designed using the reconfigurable multiplier, fault tolerant adder and Flip Flop. The implementation was carried out in Quartus Tool for different FPGA kits designed with 90nm and 65nm CMOS technology. Parameters like LUT, power dissipation and delay are investigated. The proposed approach is suitable for portable devices.

This paper proposes reversible circuit designs of the three most commonly used adders: carry look-ahead adder (CLA adder), ripple carry adder (RCA adder), and parallel adder/subtractor. The n-bit reversible CLA adder, called CLA-GH, is designed using the Peres and Fredkin gates. The n-bit optimized reversible RCA adder, called ORCA-GH, is designed using the reversible circuit of a parity-preserving reversible full adder. Both circuits reduce the quantum cost. However, the ORCA-GH circuit also improves the number of constant inputs. Furthermore, the n-bit reversible parallel adder/subtractor, called PAS-GH, is designed using the Feynman, Peres, and Fredkin gates. It decreases the number of garbage outputs and quantum cost. The transistor realizations of the CLA-GH and PAS-GH circuits are provided accordingly. The evaluation results indicate that the proposed circuits surpass the existing works in all figures of merit.