CPU

Cloud computing is a new paradigm that offers computing resources in a virtualized way with unprecedented levels of flexibility, reliability, and scalability. The benefits of cloud computing, however, come at a high cost in terms of energy consumption, mainly because of one of the cloud's core enablers, the data center. There are a number of proposals that seek to enhance the energy efficiency of data centers. Still, most of them focus on the energy consumed by CPU and ignore other important hardware components, e.g., RAM. In this paper, we show the considerable impact that RAM can have on the total energy consumption, particularly in servers with large amounts of this memory. We then propose two new approaches for dynamic consolidation of virtual machines in cloud data centers that take into account both CPU and RAM usage. We have implemented and evaluated our proposals in the CloudSim simulator using real-world traces and compared the results with other state-of-the-art soluti...

ABSTRACT Central Processing Units (CPUs) are task-parallel, latency-oriented processors, while Graphics Processing Units (GPUs) are data-parallel, throughput oriented processors. Besides their traditional use as graphics coprocessors, the GPUs have been used in recent years for general purpose computations, too. Rapid development of graphics hardware led to an extensive use in both scientific and commercial applications. Numerous papers report high speedups in various domains. This paper presents an effort to bring GPU computing closer to programmers and wider community of users. GPU computing is explored through NVIDIA Compute Unified Device Architecture (CUDA) that is currently the most mature application programming interface (API) for general purpose computation on GPUs.

Cloud computing is a new paradigm that offers computing resources in a virtualized way with unprecedented levels of flexibility, reliability, and scalability. The benefits of cloud computing, however, come at a high cost in terms of energy consumption, mainly because of one of the cloud's core enablers, the data center. There are a number of proposals that seek to enhance the energy efficiency of data centers. Still, most of them focus on the energy consumed by CPU and ignore other important hardware components, e.g., RAM. In this paper, we show the considerable impact that RAM can have on the total energy consumption, particularly in servers with large amounts of this memory. We then propose two new approaches for dynamic consolidation of virtual machines in cloud data centers that take into account both CPU and RAM usage. We have implemented and evaluated our proposals in the CloudSim simulator using real-world traces and compared the results with other state-of-the-art solutions. By adopting a wider view of the system, our proposals can reduce not only energy consumption but also service level agreement (SLA) violations, thus providing a better service at a lower cost.

Process scheduling means allocating a certain amount of CPU time to each of the user Processes. This paper proposes a CPU Scheduling algorithm, which is meant for optimizing CPU scheduling for real time applications. It is a new approach, which uses the concept of Mean Difference Round Robin (MDRR) with dynamic time quantum, whose value changes for each cycle. It acts better than RR and Mean Difference Round Robin (MDRR) Algorithm in terms of reducing the number of context switches, average waiting time and average turnaround time. The experimental results of the proposed algorithm have been compared with Mean-Difference Round Robin (MDRR) Algorithm is found to have produced optimum scheduling.

This paper deals with the modelling of a CPU-GPU chip embedded in an Android phone. The model is used for the estimation of variables that characterise the operating state of System on Chip (SoC). The proposed model is built to demonstrate the causal relationships between the variables, through its interconnected structure of subsystems. This structure allows the extension of other components or the easy exchange of subsystems in the case of a change in components or operating mode. The model developed here requires no additional instrumentation—other than the one present on the phone—which facilitates its implementation. It is used for the estimation of the state of the system and can also be used for monitoring and behaviour prediction. The model is validated and the results are promising for further implementation.

Nowadays the typical desktop computer processors have four or more independent CPU core, which are called as multi-core processors to execute instructions. So parallel programming language come into play to execute instructions concurrently for multi core architecture using openMP. Users prefer cryptographic algorithms to encrypt and decrypt data in order to send it securely over an unsafe environment like the internet. This paper describes the implementation and test results of Caesar cipher and RSA cryptographic algorithms in parallelization are done using OpenMP API 3.1 Standard and performance Analysis. According to our test results, the parallel design approach for security algorithm exhibits improved performance over the sequential approach in terms of execution of time

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported.

ABSTRACT Efficiency of energy usage in computing systems improves, however, still not at the rate matching the climbing demand for computing capacity. To address this urging problem, computing elements of the latest generation, that is, CPUs/graphics processing units, memory units, and network interface cards, have been designed to operate in multiple modes with differentiated energy consumption levels. Mode switching and high-frequency performance monitoring functions have also been exposed by co-designed abstract programming interfaces. The challenge of energy-efficient computing is to develop hardware control mechanisms taking advantage of the new capabilities. This paper aims at giving an insight into the structure of optimal energy-aware CPU frequency scaling rules. It gives a characterization of solutions to the optimal control problem of energy-efficient real-time packet inspection performed by a Linux server. A class of CPU frequency switching rules, exploiting dynamic voltage and frequency scaling mechanisms, is constructed based on experimentally identified model of server operations. The control rules are demonstrated to outperform the default CPU frequency scaling governor for the Linux kernel, both in terms of achievable power savings and service quality.

Developing efficient embedded vision applications requires exploring various algorithmic optimization trade-offs and a broad spectrum of hardware architecture choices. This makes navigating the solution space and finding the design points with optimal performance trade-offs a challenge for developers. To help provide a fair baseline comparison, we conducted comprehensive benchmarks of accuracy, run-time, and energy efficiency of a wide range of vision kernels and neural networks on multiple embedded platforms: ARM57 CPU, Nvidia Jetson TX2 GPU and Xilinx ZCU102 FPGA. Each platform utilizes their optimized libraries for vision kernels (OpenCV, VisionWorks and xfOpenCV) and neural networks (OpenCV DNN, TensorRT and Xilinx DPU). For vision kernels, our results show that the GPU achieves an energy/frame reduction ratio of 1.1-3.2× compared to the others for simple kernels. However, for more complicated kernels and complete vision pipelines, the FPGA outperforms the others with energy/frame reduction ratios of 1.2-22.3×. For neural networks [Inception-v2 and ResNet-50, ResNet-18, Mobilenet-v2 and SqueezeNet], it shows that the FPGA achieves a speed up of [2.5, 2.1, 2.6, 2.9 and 2.5]× and an EDP reduction ratio of [1.5, 1.1, 1.4, 2.2 and 1.5]× compared to the GPU FP16 implementations, respectively.

—In this paper, we have proposed a model that will help in improving the CPU scheduling of a uni-processor system. The model will use Bayesian Decision Theory as classifier tool that will select an appropriate process from a ready queue. This selection process consists of a two phases; in the first phase its compares the static and dynamic properties of the new processes in the queue with the properties of dataset of the previously executed processes. The dataset is divided into two categories of processes; useful processes and not-useful processes. The new process will be categorized as either useful or not-useful depending on the results of comparison of properties. Our proposed model is applicable in the low-level language such as Assembly at kernel level. Unix/Linux are the better platform for the implementation of our model because Linux/Unix environments are open source and their kernels are editable.

Efficiency of energy usage in computing systems improves, however, still not at the rate matching the climbing demand for computing capacity. To address this urging problem, computing elements of the latest generation, that is, CPUs/graphics processing units, memory units, and network interface cards, have been designed to operate in multiple modes with differentiated energy consumption levels. Mode switching and high-frequency performance monitoring functions have also been exposed by co-designed abstract programming interfaces. The challenge of energy-efficient computing is to develop hardware control mechanisms taking advantage of the new capabilities. This paper aims at giving an insight into the structure of optimal energy-aware CPU frequency scaling rules. It gives a characterization of solutions to the optimal control problem of energy-efficient real-time packet inspection performed by a Linux server. A class of CPU frequency switching rules, exploiting dynamic voltage and frequency scaling mechanisms, is constructed based on experimentally identified model of server operations. The control rules are demonstrated to outperform the default CPU frequency scaling governor for the Linux kernel, both in terms of achievable power savings and service quality.

With increasing core-count, the cache demand of modern processors has also increased. However, due to strict area/power budgets and presence of poor data-locality workloads, blindly scaling cache capacity is both infeasible and ineffective. Cache bypassing is a promising technique to increase effective cache capacity without incurring power/area costs of a larger sized cache. However, injudicious use of cache bypassing can lead to  bandwidth congestion and increased miss-rate and hence, intelligent techniques are required to harness its full potential. This paper presents a survey of cache bypassing techniques for CPUs, GPUs and CPU-GPU heterogeneous systems, and for caches designed with SRAM, non-volatile memory (NVM) and die-stacked DRAM. By classifying the techniques based on key parameters, it underscores their differences and similarities. We hope that this paper will provide insights into cache bypassing techniques and associated tradeoffs and will be useful for computer architects, system designers  and other researchers.

Il software, sinteticamente inteso come sequenza di istruzioni informatiche per eseguire funzioni su dispositivi
hardware, rientra nell’ambito delle immobilizzazioni immateriali e presenta, per la sua pervasività
nella vita quotidiana, uno strumento ormai irrinunciabile per qualsiasi fruitore.Ne derivano problematiche
giuridiche assai articolate, qui richiamate in sintesi, e anche sofisticati metodi di valutazione economica,
anche al fine della stima del danno da contraffazione, in uno scenario evolutivo caratterizzato da forti discontinuità
tecnologiche.

Membahas lebih lanjut atau lebih rinci tentang apa itu processor dan menilik akan fungsi processor yang banyak mengatakan sebagai otak atau pusat pengendali sebuah komputer.

Tidak hanya itu saja, ada juga contoh processor yang didalami yakni Nvidia Tegra dan Qualcomm Snapdragon, di mana kedua processor tersebut cukup dominan digunakan oleh vendor elektronik belakangan ini.

—Multi-thread architectures are the current trends for both PCs (multi-core CPUs and GPUs) and game consoles such as the Microsoft Xbox 360 and Sony Playstation 3. GPUs (Graphics Processing Units) have evolved into extremely powerful and flexible processors, allowing its use for processing different data. This advantage can be used in game development to optimize the game loop. As reported in the literature, GPGPUs have been used in processing some steps of the game loop, while most of the game logic is still processed by the CPU. This proposal differs by presenting an architecture designed to process practically the entire game loop using the GPU. Two test cases, a crowd simulation and a 2D game shooter prototype called GpuWars, are presented to illustrate the proposed architecture.

Advanced Micro Devices or AMD has been officially crowned as king of the CPU market with the Launch of Ryzen by beating their cutthroat competitors INTEL which was considered to be the giants of the CPU market until the comeback of AMD in 2018s. A brief description at the start of the research reflects the failures in the working of bulldozer CPUs which was released by AMD in the 2010s which strengthens INTEL's monopoly in the Technology market for the upcoming decade. This paper highlights the changes made by CEO Lisa Su along with Sir Jim Keller head of architecture in the working of the company and the introduction of ZEN CPUs which changed the whole perspective of performance in low budgets devices. Furthermore, the research emphasis the blunders made by Intel on having no further advancements in their expensive CPUs which was a setback for their customers. It further highlights the working of basic CPUs and then comparing the performance per dollar of the latest CPUs released by AMD with their Intel counterparts. This research lastly tries to cover the future scope of innovations in the field that will change the computing experiences or probably the working of the computers for the upcoming generations.

Recent years have witnessed a phenomenal growth in the computational capabilities and applications of GPUs. However, this trend has also led to dramatic increase in their power consumption. This paper surveys research works on analyzing and improving energy efficiency of GPUs. It also provides a classification of these techniques on the basis of their main research idea. Further, it attempts to synthesize research works which compare energy efficiency of GPUs with other computing systems, e.g. FPGAs and CPUs. The aim of this survey is to provide researchers with knowledge of state-of-the-art in GPU power management and motivate them to architect highly energy-efficient GPUs of tomorrow.

FabScalar is a toolset for automatically generating synthesizable register-transfer-level (RTL)
descriptions of arbitrary superscalar cores within a canonical superscalar template. The cores differ in
three major superscalar dimensions: fetch/issue widths, pipeline depth, and sizes of units involved in
exposing instruction-level parallelism (ILP) (issue queue, load and store queues, physical register file,
reorder buffer, etc.)

Support for multimedia applications by general purpose computing platforms has been the subject of considerable research. Much of this work is based on an evolutionary strategy in which small changes to existing systems are made. The approach adopted is to start ab initio with no backward compatibility constraints. This leads to a novel structure for an operating system. The structure aims to decouple applications from one another and to provide multiplexing of all resources, not just the CPU, at a low level. The motivation for this structure, a design based on the structure, and its implementation on a number of hardware platforms is described

Internet enabled wireless devices continue to proliferate and are expected to surpass traditional Internet clients in the near future. This has opened up exciting new opportunities in the mobile e-commerce market. However, data security and privacy remain major concerns in the current generation of "wireless Web" offerings. All such offerings today use a security architecture that lacks end-to-end security. This unfortunate choice is driven by perceived inadequacies of standard Internet security protocols like SSL (secure sockets layer) on less capable CPUs and low-bandwidth wireless links. This paper presents our experiences in implementing and using standard security mechanisms and protocols on small wireless devices. Our results show that SSL is a practical solution for ensuring end-to-end security of wireless Internet transactions even within todays technological constraints.

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported.