Leakage Energy Saving

Modern processors are using increasingly larger sized on-chip caches. Also, with each CMOS technology generation, there has been a significant increase in their leakage energy consumption. For this reason, cache power management has become a crucial research issue in modern processor design. To address this challenge and also meet the goals of sustainable computing, researchers have proposed several techniques for improving energy efficiency of cache architectures. This paper surveys recent architectural techniques for improving cache power efficiency and also presents a classification of these techniques based on their characteristics. For providing an application perspective, this paper also reviews several real-world processor chips that employ cache energy saving techniques. The aim of this survey is to enable engineers and researchers to get insights into the  techniques for improving cache power efficiency and motivate them to invent novel solutions for enabling low-power operation of caches.

"With increasing number of on-chip cores and CMOS scaling, the size of last level caches (LLCs) is on rise and hence, managing their leakage energy consumption has become vital for continuing to scale performance. In multicore systems, the locality of memory access stream is significantly reduced due to multiplexing of access streams from different running programs and hence, leakage energy saving techniques such as decay cache, which rely on memory access locality, do not save large amount of energy. The techniques based on way level allocation provide very coarse granularity and the techniques based on offline profiling become infeasible to use for large number of cores.

We present MASTER, a multicore cache energy saving technique using dynamic cache reconfiguration. MASTER uses online profiling to predict energy consumption of running programs at multiple LLC sizes. Using these estimates, suitable cache quotas are allocated to different programs using cache coloring scheme and the unused LLC space is turned off to save energy. Even for 4 core systems, the implementation overhead of MASTER is only 0.8% of L2 size. We evaluate MASTER using out-of-order simulations with multiprogrammed workloads from SPEC2006 and compare it with conventional cache leakage energy saving techniques. The results show that MASTER gives highest saving in energy and does not harm performance or cause unfairness. For 2 and 4-core simulations, the average savings in memory subsystem (which includes LLC and main memory) energy over shared baseline LLC are 15% and 11%, respectively. Also, the average values of weighted speedup and fair speedup are close to one (>=0.98)."

Recent trends of CMOS technology scaling and wide-spread use of multicore processors
have dramatically increased the power consumption of main memory. It has been
estimated that modern data-centers spend more than 30% of their total power
consumption in main memory alone. This excessive power dissipation has created the
problem of “memory power wall” which has emerged as a major design constraint
inhibiting further performance scaling. Recently, several techniques have been proposed
to address this issue. The focus of this paper is to survey several architectural techniques
designed for improving power efficiency of main memory systems, specifically DRAM
systems. To help the reader in gaining insights into the similarities and differences between
the techniques, this paper also presents a classification of the techniques on the basis of
their characteristics. The aim of the paper is to equip the engineers and architects with
knowledge of the state of the art DRAM power saving techniques and motivate them to
design novel solutions for addressing the challenges presented by the memory power wall
problem.

"Leakage energy has been estimated to increase by
five-times with each CMOS technology generation and this
is expected to become a major source of energy dissipation,
especially in large last-level caches (LLCs). We present EnCache,
a novel cache leakage energy saving scheme that uses a new
micro-architecture component called profiling cache. With this
hardware support, system software can accurately predict the
cache usage and energy efficiency of a running program for 32
possible cache configurations and vary the cache configuration
for saving cache leakage power. Unlike existing schemes, En-
Cache can directly optimize for the overall memory subsystem
power efficiency instead of only cache power efficiency. EnCache employs dynamic performance regulation and hence does not require offline profiling or per-application tuning. The experiments performed over our workload confirm the superiority of EnCache scheme over conventional energy-saving schemes. On a baseline configuration of 2MB cache size, the average improvement of memory subsystem energy and energy-delay-product (EDP) by using EnCache are 31.7% and 28.8%, respectively."

With each CMOS technology generation, leakage energy consumption has been dramatically increasing and hence,  managing leakage power consumption of large last-level caches (LLCs) has become a critical issue in modern processor design.  In this paper, we present EnCache, a novel software-based technique which uses dynamic profiling-based cache reconfiguration for saving cache leakage energy. EnCache uses a simple hardware component called profiling cache, which dynamically predicts energy efficiency of an application for 32 possible cache configurations. Using these estimates, system software reconfigures the cache to the most energy efficient configuration. EnCache uses dynamic cache reconfiguration and hence, it does not require offline profiling or tuning the parameter for each application. Furthermore, EnCache optimizes directly for the overall memory subsystem (LLC and main memory)
energy efficiency instead of the LLC energy efficiency alone. The experiments performed with an x86-64 simulator and workloads from SPEC2006 suite confirm that EnCache provides larger energy saving than a conventional energy saving scheme. For single core and dual-core system configurations, the average savings in memory subsystem energy over a shared baseline configuration are 30.0% and 27.3%, respectively.

With each CMOS technology generation, leakage energy has been increasing at an exponential rate. Since modern processors employ large last level caches (LLCs), their leakage energy consumption has become an important concern in modern chip design. To address this issue, several techniques have been proposed. However, most of these techniques require offline profiling and hence, cannot be used in real-life systems which run trillions of instructions of arbitrary applications. In this paper, we propose Palette, a technique for saving cache leakage energy using cache coloring. Palette uses a small hardware component called reconfigurable cache emulator, to estimate performance and energy consumption of multiple cache configurations and then selects the configuration with least energy consumption. Simulations performed with SPEC2006 benchmarks show the superiority of Palette over existing cache energy saving technique. With a 2MB baseline cache, the average saving in memory sub-system energy and EDP (energy delay product) are 31.7% and 29.5%, respectively.