STTRAM

—Spin-Transfer Torque RAM (STT-RAM) has emerged as a potential candidate for universal memory. An electrical model of STT-RAM cell is needed to adequately explore the design space of the device. In this paper, a comprehensive and compact Verilog-A behavioral model of STT-RAM cell is presented. The model captures both dynamic switching aspects and static properties of the magnetic tunnel junction (MTJ), which is the basic storage device in the STT-RAM cell. The dynamic switching behavior is modeled using Bernoulli random binary number generator in combination with switching probability function. The static behavior was represented by means of a variable resistor with bias current/voltage dependent low-and high-resistance values. In addition to its compactness and comprehensiveness, the model is suited to be used within standard integrated circuit CAD tools for analog and mixed-signal design simulation.

[For clarity, the same information has been put in the pdf file uploaded]        The code can be downloaded from https://code.ornl.gov/3d_cache_modeling_tool/destiny . The technical report is here http://goo.gl/qzyWFE, which is extension of our DATE 2015 paper http://goo.gl/3nKAM2. The manual for DESTINY tool is here https://code.ornl.gov/3d_cache_modeling_tool/destiny/blob/master/Doc/DESTINY_Documentation.pdf