VLSI CAD

Emerging semiconductor VLSI requires improved device density on a single chip solution that many parameters are becoming vital concern for cost reduction by lowering the chip area, lowering power dissipation, reducing operating voltage, increasing speed etc. A previously designed precision sensor application mirror-amplifier was considered for optimizing in chip area consumption and improves sensing to make it ultra-precise, also this work has reduced the IC to a subcompact die sizes. MAGIC is used as two-dimensional CAD layout tool. Also PSPICE is used for electrical simulation purposes employed by extraction tool. Feature size is taken from mSCN3M_SUBM.30 process for 0.6µm layout and 0.5µm enhanced fabrication process. The improved design has area of 101λX48λ (minimized from 126λX59λ) or 30.3µmX15µm (minimized from 37.8µmX17.7µm) in 0.6µm CMOS design process. For multi-die placement, two sets of chip are designed those are placed on the four sub-dies in a single MOSIS tinychip die. For one set of chip coincidence detector is designed to make the mirror-amplifier ultra precise, buffer stage is designed for another set of chip to drive large load. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.

— In this paper, we introduce a method for realizable reduction of extracted RC netlists by merging nodes. This method can achieve high reduction (reaching 96%) with high accuracy and can be used to complement existing techniques of realizable reduction such as TICER [6]. The method preserves sparsity; has controllable accuracy and can result in lossless reduction (exact reduction) for certain circuits. The node merging translates to a simple matrix operation and thus can be easily adopted commercially and realized in CAD tools.

This paper presents an efficient architecture for various image filtering algorithms and tumor characterization using Xilinx System Generator (XSG). This architecture offers an alternative through a graphical user interface that combines MATLAB, Simulink and XSG and explores important aspects concerned to hardware implementation. Performance of this architecture implemented in SPARTAN-3E Starter kit (XC3S500E-FG320

Electrical Engineering: An International Journal (EEIJ) is a Quarterly peer-reviewed and refered open access journal that publishes articles which contribute new results in all areas of Electrical Engineering. The journal is devoted to the publication of high quality papers on theoretical and practical aspects of Electrical Engineering.

En este trabajo se desarrolla los conceptos de un sistema VLSI, los cuales representan a la mayoría de los microchips de hoy en día. Pasaremos por la historia de los chips de computadoras viendo su evolución en el tiempo y el pronóstico para el futuro. Se mostrarán los distintos componentes que componente un chip y como estos son implementados en la fabricación a VLSI.

12th International Conference on Embedded Systems and Applications (EMSA 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Embedded Systems. The goal of this Conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern Embedded Systems concepts and establishing new collaborations in these areas.

2nd International Conference on VLSI & Embedded Systems (VLSIE 2021) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of VLSI and Embedded Systems. Original, unpublished papers, describing research in the general area of VLSI and Embedded Systems are solicited. Both theoretical and experimental research results are welcome in the following areas, but are not limited to.

This paper describes the design of FPGA based signal processing card. An on board real time digital signal processing system is designed using FPGA. The platform can decode process of various kinds of digital and analog signals simultaneously. The design trend in this card is towards small size, high integration and fast real time processing. For the optimum performance a 16 bit 1 MSPS ADC is used which is interfaced with FPGA to make all the data processing onboard in real time. This card can be used in many signal processing based applications like audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications by interfacing several separate board using inbuilt I/O's, each with a number of input channels that will communicate with each other in real time over a high speed communication link. The resulting images can be displayed directly on LCD or OLED panel displays using I/O's peripherals. The project introduces many challenging issues, which are being addressed in turn with different prototype designs. These issues are the ADC performance, interfacing the ADCs to the FPGA, implementing the flexible processing algorithms and high speed interconnection between the boards.

Development of VLSI is a unique era in microelectronics, more precisely in integrated circuit industry. VLSI is the field which involves packing more and more logic devices into smaller areas combining thousands or many more than that of transistors into a single chip. But the design of very large scale integrated circuit is far beyond human ability. Therefore, Computer Aided Design (CAD) tools are heavily involved in the design process. This is highly expensive and technological at the same time. Unfortunately 3rd world countries are lagging far behind in this arena. This study represents a brief demonstration on one of the VLSI designing CAD tools known as MAGIC. The study includes a brief and precise direction from the software installation to the way of IC fabrication with a design of CMOS inverter and its simulation as example. It also includes why MAGIC should be the choice in academic purpose as well as industrial especially in 3rd world countries, along with its limitations and superiority.

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called " XOR (3T) " is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP). .

In today’s VLSI field the exponentially increasing factor of integration takes the techniques of chip designing to be more cared about both switch level (eg. device, logic gate design, etc.) and chip level (eg. pad design, floorplanning, routing, etc.) as size of chip is continually decreasing and power consumption challenge is getting tougher. To design a complete & successful functional chip, pad frame design and floorplanning are also challenging. This study is an attempt to present a VLSI design of pad frame with less power consuming I/O architecture with an efficient way of floorplanning which includes block placement, global routing, detail routing. MAGIC is used as layout designing CAD tool to design the pad frame as it is the easiest and worldwide CAD tool for VLSI layout design, and for simulation purpose PSpice is used. This study presents details of the key research work, results, techniques and efficient way of pad frame design as well as floorplanning.

11th International Conference on Embedded Systems and Applications (EMSA 2022) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Embedded Systems. The goal of this Conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern Embedded Systems concepts and establishing new collaborations in these areas.

Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal's bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC) and Digital Down Conversion (DDC) are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock frequency. Both the designs have passed postroute delay based simulations, static performance checks, power domain checks and TSMC's 65nm design rule checks.

VLSI IEEE Projects 2017 | IEEE 2018 VLSI Project Titles
IEEE 2017-18 VLSI Project Titles
LOW POWER
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
Resource-Efficient SRAM-based Ternary Content Addressable Memory
Write-Amount-Aware Management Policies for STT-RAM Caches
Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
Efficient Designs of Multi-ported Memory on FPGA
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock
A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares
Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm
A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission
Scalable Device Array for Statistical Characterization of BTI-Related Parameters
AREA EFFICIENT/ TIMING & DELAY REDUCTION
VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs
Efficient Soft Cancelation Decoder Architectures for Polar Codes
Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers
Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields
Antiwear Leveling Design for SSDs With Hybrid ECC Capability
Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems
Audio, Image and Video Processing
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations
Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
An FPGA-Based Hardware Accelerator for Traffic Sign Detection
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations
Time-Encoded Values for Highly Efficient Stochastic Circuits
Design of Power and Area Efficient Approximate Multipliers
VERIFICATION
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction
NETWORKING
Multicast-Aware High-Performance Wireless Network-on-Chip Architectures
VLSI - BACK END PROJECT - TANNER(nm) / HSPICE(nm) / DSCH3 - MICROWIND(um)
Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures
Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
Delay Analysis for Current Mode Threshold Logic Gate Designs
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS
Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application
An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz
A 65-nm CMOS Constant Current Source with Reduced PVT Variation
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy
Preweighted Linearized VCO Analog-to-Digital Converter
A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression
Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template
On Micro-architectural Mechanisms for Cache Wear out Reduction
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology
A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing
A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures

This paper presents routing in VLSI chips which is broken into two distinct processes : Global routing & Detailed routing. We have provided a brief review of these routing techniques & their implementation. In VLSI design flow after placement, the routing process determines the precise paths for nets on the chip layout to interconnect the pins on the circuit blocks or pads at the chip boundary. These precise paths of nets must satisfy the design rules provided by chip foundries to ensure that the designs can be correctly manufactured. Routing is to complete all the required connections to achieve 100% routability otherwise, the chip would not function well and may even fail. There are routing problems due to constraints on the number of wires that can pass through the channel.

International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

A significant portion of the total power consumption in high performance digital circuits in deep sub-micron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates.. All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

Memristors, usually in the form metal/metal-oxide/metal, have attracted much attention due to their potential application
for non-volatile memory. Their simple structure and ease of fabrication make them good candidates for dense memory
with projections of 22 terabytes per wafer. Excellent switching times of ~10 ns, memory endurance of >109 cycles, and
extrapolated retention times of >10 yrs have been reported. Interestingly, memristors use the migration of ions to change
their resistance in response to charge flow, and can therefore measure and remember the amount of current that has
flowed. This is similar to many MEMS devices in which the motion of mass is an operating principle of the device.
Memristors are also similar to MEMS in the sense that they can both be resistant to radiation effects. Memristors are
radiation tolerant since information is stored as a structural change and not as electronic charge. Functionally, a MEMS
device’s sensitivity to radiation is concomitant to the role that the dielectric layers play in the function of the device. This
is due to radiation-induced trapped charge in the dielectrics which can alter device performance and in extreme cases
cause failure. Although different material systems have been investigated for memristors, SnO2 has received little
attention even though it demonstrates excellent electronic properties and a high resistance to displacement damage from
radiation due to a large Frenkel defect energy (7 eV) compared its bandgap (3.6 eV). This talk discusses recent research
on SnO2-based memristors and the potential synergies of integrating memristors with MEMS.
Keywords: Memristors, MEMS, radiation-hard, integration, SnO2

Autodesk Revit is the observable Building Information Modeling (BIM) application, used to make sensible setup of a building including its parts and sub-sections. The clients of Autodesk Revit for most part incorporates experts and modelers (planners) empowering them to make 3d blueprint structures and managing database frameworks to get the structural information. In addition Revit MEP is developed application getting a handle on the masses inside the arranging and building setup field.

In  this  paper  the  use  of  artificial  neural  network  in  power  system  stability  is  studied.  A  predictive
controller  based  on  two  neural  networks  is  designed  and  tested  on a  single  machine  infinite  bus  system
which  is  used  to  replace  conventional  power  system  stabilizers.  They  have  been  used  for  decades  in
power  system  to  dampen  small  amplitude  low  frequency  oscillation  in  power  systems.  The  increases  in
size  and  complexity  of  power  systems  have  cast  a  shadow  on  efficiency  of  conventional  method.  New
control strategies have been proposed in many researches. Artificial Neural Networks have been studied
in many publications but lack of assurance of their functionality has hindered the practical usage of them
in utilities. The proposed control structure is modelled using a novel data exchange established between
MATLAB  and  DIgSILENT  power  factory.  The  result  of  simulation  proves  the  efficiency of  the  proposed
structure.

The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.

This paper determines the propagation delay and on chip power consumed by each basic and universal gates and basic arithmetic functions designed using existing reversible gates through VHDL. Hence a designer can choose the best reversible gates to use for any logic circuit design. The paper does a look up table analysis of truth tables of the reversible gates to find the occurrence of the AND OR, NAND, NOR and basic arithmetic functions, useful to build complex combinational digital logic circuits.

wordpress.com/ Scope & Topics Electrical Engineering: An International Journal (EEIJ) is a Quarterly peer-reviewed and refered open access journal that publishes articles which contribute new results in all areas of Electrical Engineering. The journal is devoted to the publication of high quality papers on theoretical and practical aspects of Electrical Engineering.

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix-2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC. KEYWORDS Radix-2 modified booth algorithm, Digital signal processing, spurious power suppression Technique, Verilog.

Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an optimized and dedicated hardware. The real time implementation places several constraints such as area occupied, power consumption , etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression sequence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.

Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.

To date, the best algorithms for performing placement on Field-Programmable Gate Arrays (FPGAs) are based on Simulated Annealing (SA). Unfortunately, these algorithms are not scalable due to the long convergence time of the latter. With an aim towards developing a scalable FPGA placer we present an analytic placement method based on a near-linear net model, called star +. The star + model is a variant of the well-known star model and is continuously differentiable – a requirement of analytic methods that rely on the existence of first-and second-order derivatives. Most importantly, with the star + model incremental changes in cost resulting from block movement can be computed in O(1) time, regardless of the size of the net. This makes it possible to construct time-efficient solution methods based on conjugate gradient and successive over-relaxation for solving the resulting non-linear equation system. When compared to VPR, the current state-of-the-art placer based on SA, our analytic method is able to obtain an 8–9% reduction in critical-path delay while achieving a speedup of nearly 5x when VPR is run in its fast mode. Crown

This paper determines the propagation delay and on chip power consumed by each basic and universal gates and basic arithmetic functions designed using existing reversible gates through VHDL. Hence a designer can choose the best reversible gates to use for any logic circuit design. The paper does a look up table analysis of truth tables of the reversible gates to find the occurrence of the AND OR, NAND, NOR and basic arithmetic functions, useful to build complex combinational digital logic circuits.

The transmission lines structures are quite common in the system of electromagnetic compatibility (EMC)
analysis. The increasing complexities of physical structures make electromagnetic modeling an
increasingly  tough  task,  and  computational  efficiency  is  desirable.  In  this  paper,  a  novel  selective  mesh
approach is presented for partial element equivalent circuit (PEEC) modeling where intense coupling parts
are  meshed  while  the  remaining  parts  are  eliminated.  With  the  proposed  approach,  the  meshed  ground
plane is dependent on the length and height of the above transmission lines. Relevant compact formulae for
determining  mesh  boundaries  are  deduced,  and  a  procedure  of  general  mesh generation  is  also  given.  A
numerical example is presented, and a validation check is accomplished, showing that the approach leads
to  a  significant  reduction  in  unknowns  and  thus  computation  time  and  consumed  memories,  while
preserving  the  sufficient  precision.  This  approach  is  especially  useful  for  modeling  the  electromagnetic
coupling  of  transmission  lines  and  reference  ground,  and  it  may  also  be  beneficial  for  other  equivalent
circuit modeling techniques.

In this paper, a scheme for the design of area efficient and high speed pipeline VLSI architecture for the computation of fixed point 1-d discrete wavelet transform using lifting scheme is proposed. The main focus of the scheme is to reduce the number and period of clock cycles and efficient area with little or no overhead on hardware resources. The fixed point representation requires less hardware resources compared with floating point representation. The pipelining architecture speeds up the clock rate of DWT and reduced bit precision reduces the area required for implementation. The architecture has been coded in verilog HDL on Xilinx platform and the target FPGA device used is Virtex-II Pro family, XC2VP7-7board. The proposed scheme requires the least computing time for fixed point 1-D DWT and achieves the less area for implementation, compared with other architectures. So this architecture is realizable for real time processing of DWT computation applications. KEYWORDS Discrete wavelet transform (DWT), Lifting based scheme, field-programmable gate-array (FPGA), pipeline architecture, reduced bit precision, fixed point, VLSI architecture.