Matt Francis

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This paper presents the first operational digital to analog converter at 400°C. The 8 bit R-2R ladder DAC was designed in the Raytheon 1.2 μm CMOS HiTSiC process. The data converter is also the first of its kind in SiC. It has been tested with a supply voltage between 12 V and 15 V, and reference voltages of 5 V to 8 V. At 400°C, the maximum measured differential non linearity (DNL) is 2 LSB (least significant bit) and the integral non linearity is… Show more

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This paper presents the first operational digital to analog converter at 400°C. The 8 bit R-2R ladder DAC was designed in the Raytheon 1.2 μm CMOS HiTSiC process. The data converter is also the first of its kind in SiC. It has been tested with a supply voltage between 12 V and 15 V, and reference voltages of 5 V to 8 V. At 400°C, the maximum measured differential non linearity (DNL) is 2 LSB (least significant bit) and the integral non linearity is 4.4 LSB. Show less

This paper demonstrates the first reported high temperature voltage comparator in
CMOS silicon carbide. The comparator was designed in a 1.2 µm CMOS SiC process and
has been tested for a voltage supply of 12 V to 15 V. The rail to rail voltage comparator has
been tested up to 450 C with rise and fall times of 31 ns and 22 ns respectively, and positive
and negative propagation delays of 108 ns and 107 ns respectively. Keywords—
comparator, silicon carbide, high temperature… Show more

This paper demonstrates the first reported high temperature voltage comparator in
CMOS silicon carbide. The comparator was designed in a 1.2 µm CMOS SiC process and
has been tested for a voltage supply of 12 V to 15 V. The rail to rail voltage comparator has
been tested up to 450 C with rise and fall times of 31 ns and 22 ns respectively, and positive
and negative propagation delays of 108 ns and 107 ns respectively. Keywords—
comparator, silicon carbide, high temperature electronics, wide bandgap ICs. Show less

This paper describes the simulation and test results of a family of analog and mixed signal circuits in silicon carbide CMOS technology at temperatures of 300°C and above. As SiC and wide bandgap devices in general grow in popularity for efficient and stable operation in high temperature and harsh environment applications, CMOS SiC integrated circuits can open up a new frontier of opportunity for miniaturization and system dependability. The building block circuits presented here can serve as… Show more

This paper describes the simulation and test results of a family of analog and mixed signal circuits in silicon carbide CMOS technology at temperatures of 300°C and above. As SiC and wide bandgap devices in general grow in popularity for efficient and stable operation in high temperature and harsh environment applications, CMOS SiC integrated circuits can open up a new frontier of opportunity for miniaturization and system dependability. The building block circuits presented here can serve as the basis of rugged SiC system-on-chips for extreme environment applications. Show less

This paper describes the simulation and test results of a family of analog and mixed signal circuits in silicon carbide CMOS technology at temperatures of 300°C and above. As SiC and wide bandgap devices in general grow in popularity for efficient and stable operation in high temperature and harsh environment applications, CMOS SiC integrated circuits can open up a new frontier of opportunity for miniaturization and system dependability. The building block circuits presented here can serve as… Show more

This paper describes the simulation and test results of a family of analog and mixed signal circuits in silicon carbide CMOS technology at temperatures of 300°C and above. As SiC and wide bandgap devices in general grow in popularity for efficient and stable operation in high temperature and harsh environment applications, CMOS SiC integrated circuits can open up a new frontier of opportunity for miniaturization and system dependability. The building block circuits presented here can serve as the basis of rugged SiC system-on-chips for extreme environment applications. Show less

A series of “standard” parts for use in extreme environments based on high-temperature silicon carbide complimentary logic is presented. High temperature results and statistical samples are used to demonstrate the maturity of the parts for extreme environment applications.

Abstract-An asynchronous NULL Convention Logic (NCL) gate library is developed for
applications in space environment with temperatures ranging from-196 C to 125 C with
radiation exposure. To further improve radiation-immunity and temperature-stability dual
high-density metal-insulator metal (DMIM) capacitor-based delay elements (using the IBM 90nm SiGe - 9HP process) were created.

The design and test of the first undervoltage lock-out circuit implemented in a low voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between… Show more

The design and test of the first undervoltage lock-out circuit implemented in a low voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 °C and 200 °C. Captured data shows the circuit to be functional over a temperature range from -55 °C to 300 °C. The design of the circuit and test results is presented. Show less

A gate buffer fabricated in a 2 um 4H silicon carbide process is presented. The circuit is composed of an input buffer stage with a push-pull output stage, and is fabricated using enhancement mode N-channel FETs in a process optimized for SiC power switching devices. Simulation and measurement results of the fabricated gate buffer are presented and compared for operation at various voltage supply levels, with a capacitive load of 2 nF. Details of the design including layout specifics… Show more

A gate buffer fabricated in a 2 um 4H silicon carbide process is presented. The circuit is composed of an input buffer stage with a push-pull output stage, and is fabricated using enhancement mode N-channel FETs in a process optimized for SiC power switching devices. Simulation and measurement results of the fabricated gate buffer are presented and compared for operation at various voltage supply levels, with a capacitive load of 2 nF. Details of the design including layout specifics, simulation results, and directions for future improvement of this buffer are presented. In addition, plans for its incorporation into an isolated high-side/low-side gate-driver architecture, fully integrated with power switching devices in a SiC process, are briefly discussed. This letter represents the first reported MOSFET-based gate buffer fabricated in 4H SiC. Show less

Multi-Chip Power Modules (MCPMs) allow for integration of high power semiconductor devices and control circuitry into one compact package which yields improved reliability and reduced size, cost, and complexity. The layout design process of an MCPM is time consuming and very multidisciplinary, spanning thermal, electrical, and mechanical issues. A software tool is introduced in this paper which allows for a user to draw a `stick figure' of a desired MCPM layout which is transformed into a… Show more

Multi-Chip Power Modules (MCPMs) allow for integration of high power semiconductor devices and control circuitry into one compact package which yields improved reliability and reduced size, cost, and complexity. The layout design process of an MCPM is time consuming and very multidisciplinary, spanning thermal, electrical, and mechanical issues. A software tool is introduced in this paper which allows for a user to draw a `stick figure' of a desired MCPM layout which is transformed into a multi-objective optimization problem by the tool. After optimization, a user can browse a set of results which form a trade-off curve of approximately Pareto optimal thermal and electrical parasitic layout performance. Show less

A single-event model capable of capturing bias-dependent effects has been
developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process
design kit. Simulation comparisons with mixed mode TCAD are presented

Single Event Transients (SETs), the choice of strike model is shown to have a notable effect
upon observed upsets. A method utilizing distributed charges to model strikes to adjacent
devices is illustrated and utilized to compare the effect of strike kernel models in such
Charge Sharing SETS (CSSETS). Bias-dependent models are shown to more accurately
predict expected physical observations and Technology Computer Aided Design (TCAD)
simulation, especially when such… Show more

Single Event Transients (SETs), the choice of strike model is shown to have a notable effect
upon observed upsets. A method utilizing distributed charges to model strikes to adjacent
devices is illustrated and utilized to compare the effect of strike kernel models in such
Charge Sharing SETS (CSSETS). Bias-dependent models are shown to more accurately
predict expected physical observations and Technology Computer Aided Design (TCAD)
simulation, especially when such charge-sharing upsets must be considered Show less