Version 1
: Received: 2 November 2021 / Approved: 4 November 2021 / Online: 4 November 2021 (11:21:35 CET)
How to cite:
Javadi, M. Developing Verification and Optimization Models for Corona Discharge Suppression in High Voltage AC and DC Capacitor Banks. Preprints2021, 2021110102. https://doi.org/10.20944/preprints202111.0102.v1
Javadi, M. Developing Verification and Optimization Models for Corona Discharge Suppression in High Voltage AC and DC Capacitor Banks. Preprints 2021, 2021110102. https://doi.org/10.20944/preprints202111.0102.v1
Javadi, M. Developing Verification and Optimization Models for Corona Discharge Suppression in High Voltage AC and DC Capacitor Banks. Preprints2021, 2021110102. https://doi.org/10.20944/preprints202111.0102.v1
APA Style
Javadi, M. (2021). Developing Verification and Optimization Models for Corona Discharge Suppression in High Voltage AC and DC Capacitor Banks. Preprints. https://doi.org/10.20944/preprints202111.0102.v1
Chicago/Turabian Style
Javadi, M. 2021 "Developing Verification and Optimization Models for Corona Discharge Suppression in High Voltage AC and DC Capacitor Banks" Preprints. https://doi.org/10.20944/preprints202111.0102.v1
Corona discharge; corona ring; corona suppression; high voltage capacitor banks; shunt capacitor banks
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.