Product Order Technical Tools & Support &

Folder Now Documents Software Community

ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

ISO1500 3-kVRMS Basic Isolated RS-485/RS-422 Transceiver in Ultra-Small Package

1 Features 3 Description
•
1 Meets or exceeds requirements of TIA/EIA-485-A The ISO1500 device is a galvanically-isolated
differential line transceiver for TIA/EIA RS-485 and
• Half-duplex transceiver RS-422 applications. This device has a 3-channel
• Low-EMI 1-Mbps data rate digital isolator and an RS-485 transceiver in an ultra-
• Bus I/O protection small 16-pin SSOP package. The bus pins of this
transceiver are protected against IEC ESD contact
– ± 16 kV HBM ESD
discharge and IEC EFT events. The receiver output
• 1.71-V to 5.5-V Logic-side supply (VCC1), 4.5-V to has a failsafe for bus open, short, and idle conditions.
5.5-V Bus-side supply (VCC2) The small solution size of ISO1500 greatly reduces
• 1/8 Unit load: up to 256 nodes on bus the board space required compared to other
• Failsafe receiver for bus open, short, and idle integrated isolated RS-485 solutions or discrete
implementation with optocouplers and non-isolated
• 100-kV/µs (typical) High common-mode transient RS-485 transceiver.
immunity
The device is used for long distance communications.
• Extended temperature range from –40°C to Isolation breaks the ground loop between the
+125°C communicating nodes, allowing for a much larger
• Glitch-free power-up and power-down for hot plug- common mode voltage range. The symmetrical
in isolation barrier of each device is tested to provide
• Ultra-small SSOP (DBQ-16) package 3000 VRMS of isolation for 1 minute per UL 1577
between the bus-line transceiver and the logic-level
• Safety-related certifications: interface.
– 4242-VPK VIOTM and 566-VPK VIORM per DIN
The ISO1500 device can operate from 1.71 V to 5.5
VDE V 0884-11:2017-01
V on side 1 which lets the devices interface with low-
– 3000-VRMS Isolation for 1 minute per UL 1577 voltage FPGAs and ASICs. The supply voltage on
– IEC 60950-1, IEC 62368-1 and IEC 61010-1 side 2 is from 4.5 V to 5.5 V. This device supports a
certifications wide operating ambient temperature range from
–40°C to +125°C.
– CQC, TUV, and CSA certifications
Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)
• Electricity meters ISO1500 SSOP (16) 4.90 mm × 3.90 mm
• Protection relay (1) For all available packages, see the orderable addendum at
• Factory automation & control the end of the data sheet.
• HVAC systems and building automation
Simplified Schematic
• Motor drives

Logic Supply Bus-Side Supply

VCC1 VCC2
VDD

DE ISO1500 A
MCU D RS485 Bus
B
R

DGND RE Isolated Ground

GND1 GND2
Logic Ground
Galvanic Isolation
Barrier

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

Table of Contents
1 Features .................................................................. 1 7 Parameter Measurement Information ................ 15
2 Applications ........................................................... 1 8 Detailed Description ............................................ 18
3 Description ............................................................. 1 8.1 Overview ................................................................. 18
4 Revision History..................................................... 2 8.2 Functional Block Diagram ....................................... 18
5 Pin Configuration and Functions ......................... 3 8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 20
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 9 Application and Implementation ........................ 22
6.2 ESD Ratings.............................................................. 4 9.1 Application Information............................................ 22
6.3 Recommended Operating Conditions....................... 4 9.2 Typical Application ................................................. 23
6.4 Thermal Information .................................................. 4 10 Power Supply Recommendations ..................... 24
6.5 Power Ratings........................................................... 5 11 Layout................................................................... 25
6.6 Insulation Specifications............................................ 6 11.1 Layout Guidelines ................................................. 25
6.7 Safety-Related Certifications..................................... 7 11.2 Layout Example .................................................... 25
6.8 Safety Limiting Values .............................................. 7 12 Device and Documentation Support ................. 27
6.9 Electrical Characteristics: Driver ............................... 8 12.1 Documentation Support ....................................... 27
6.10 Electrical Characteristics: Receiver ........................ 8 12.2 Receiving Notification of Documentation Updates 27
6.11 Supply Current Characteristics: Side 1(ICC1) .......... 9 12.3 Community Resource............................................ 27
6.12 Supply Current Characteristics: Side 2(ICC2) .......... 9 12.4 Trademarks ........................................................... 27
6.13 Switching Characteristics: Driver .......................... 10 12.5 Electrostatic Discharge Caution ............................ 27
6.14 Switching Characteristics: Receiver...................... 10 12.6 Glossary ................................................................ 27
6.15 Insulation Characteristics Curves ......................... 10 13 Mechanical, Packaging, and Orderable
6.16 Typical Characteristics .......................................... 11 Information ........................................................... 27

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (September 2019) to Revision D Page

• Added updated certification information in Safety-Related Certifications .............................................................................. 7

Changes from Revision B (May 2019) to Revision C Page

• Changed certificate related info in Features section .............................................................................................................. 1

• Added footnote to Pin function table for NC pin ..................................................................................................................... 3

Changes from Revision A (December 2018) to Revision B Page

• Added HBM ESD to feature list ............................................................................................................................................. 1

Changes from Original (September 2018) to Revision A Page

• Changed device status from Advanced Information to Production Data................................................................................ 1

2 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

5 Pin Configuration and Functions

DBQ Package
16-Pin SSOP
Top View

VCC1 1 16 VCC2

GND1 2 15 GND2

R 3 14 NC

ISOLATION
RE 4 13 B

DE 5 12 A

D 6 11 NC

NC 7 10 VCC2

GND1 8 9 GND2

Not to scale

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
A 12 I/O Transceiver noninverting input or output (I/O) on the bus side
B 13 I/O Transceiver inverting input or output (I/O) on the bus side
D 6 I Driver input
Driver enable. This pin enables the driver output when high and disables the driver output when low
DE 5 I
or open.
2
GND1 — Ground connection for VCC1
8
9
GND2 — Ground connection for VCC2
15
7
NC (1) 11 — No internal connection
14
R 3 O Receiver output
Receiver enable. This pin disables the receiver output when high or open and enables the receiver
RE 4 I
output when low.
VCC1 1 — Logic-side power supply
10 Transceiver-side power supply. These pins are not connected internally and must be shorted
VCC2 —
16 externally on PCB.

(1) Device functionality is not affected if NC pins are connected to supply or ground on PCB

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
VCC1 Supply voltage, side 1 -0.5 6 V
VCC2 Supply voltage, side 2 -0.5 6 V
VIO Logic voltage level (D, DE, RE, R) -0.5 VCC1+0.5 (3) V
IO Output current on R pin -15 15 mA
VBUS Voltage on bus pins (A, B, Y, Z w.r.t GND2) -18 18 V
TJ Junction temperature -40 150 ℃
TSTG Storage temperature -65 150 ℃

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V

6.2 ESD Ratings

VALUE UNIT
Electrostatic discharge All pins except bus pins (1) ±4000 V
Human body model (HBM), per (1)
ANSI/ESDA/JEDEC JS-001 Bus terminals to GND2 ±16000
V(ESD)
Electrostatic discharge V
Charged device model (CDM), per All pins (2) ±1500
JEDEC specification JESD22-C101

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
Supply Voltage, Side 1, 1.8-V operation 1.71 1.89 V
VCC1
Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation 2.25 5.5 V
VCC2 Supply Voltage, Side 2 4.5 5.5 V
VI Common mode voltage at any bus terminal: A or B -7 12 V
VIH High-level input voltage (D, DE, RE inputs) 0.7*VCC1 VCC1 V
VIL Low-level input voltage (D, DE, RE inputs) 0 0.3*VCC1 V
VID Differential input voltage -12 12 V
IO Output current, Driver -60 60 mA
IOR Output current, Receiver -4 4 mA
RL Differential load resistance 54 Ω
1/tUI Signaling rate 1 Mbps
TA Operating ambient temperature -40 125 °C

6.4 Thermal Information

ISO1500
THERMAL METRIC (1) DBQ (SSOP) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 112.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 57.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

Thermal Information (continued)

ISO1500
THERMAL METRIC (1) DBQ (SSOP) UNIT
16 PINS
RθJB Junction-to-board thermal resistance 64.0 °C/W
ΨJT Junction-to-top characterization parameter 32.1 °C/W
ΨJB Junction-to-board characterization parameter 63.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance -- °C/W

6.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation (both sides) VCC1 = VCC2 = 5.5 V, TA=125°C, TJ = 278 mW
150°C, A-B load = 54 Ω ||50pF, Load on
PD1 Maximum power dissipation (side-1) 28 mW
R=15pF
Input a 500kHz 50% duty cycle square
PD2 Maximum power dissipation (side-2) wave to D pin with 250 mW
VDE=VCC1, VRE=GND1

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

6.6 Insulation Specifications

SPECIFICATIONS
PARAMETER TEST CONDITIONS UNIT
DBQ-16
IEC 60664-1
(1)
CLR External clearance Side 1 to side 2 distance through air >3.7 mm
(1)
CPG External creepage Side 1 to side 2 distance across package surface >3.7 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 V
Material Group According to IEC 60664-1 I
Overvoltage category Rated mains voltage ≤ 300 VRMS I-III
DIN VDE V 0884-11:2017-01 (2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 566 VPK
AC voltage (sine wave); time-dependent
400 VRMS
VIOWM Maximum isolation working voltage dielectric breakdown (TDDB) test;
DC voltage 566 VDC
VTEST = VIOTM , t = 60 s (qualification); VTEST =
VIOTM Maximum transient isolation voltage 4242 VPK
1.2 × VIOTM, t = 1 s (100% production)
Maximum surge isolation voltage Test method per IEC 62368-1, 1.2/50 µs
VIOSM 4000 VPK
ISO1500 (3) waveform, VTEST = 10000 VPK (qualification)
Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 ≤5
s
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
≤5
(4) Vpd(m) = 1.6 × VIORM , tm = 10 s
qpd Apparent charge pC

Method b1: At routine test (100% production)

and preconditioning (type test), Vini = VIOTM, tini =
1 s; ≤5
Vpd(m) = 1.875 × VIORM , tm = 1 s

(5)
CIO Barrier capacitance, input to output VIO = 0.4 × sin (2 πft), f = 1 MHz ~1 pF
12
VIO = 500 V, TA = 25°C > 10
(5)
RIO Insulation resistance, input to output VIO = 500 V, 100°C ≤ TA ≤ 150°C > 1011 Ω
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VTEST = VISO , t = 60 s (qualification); VTEST = 1.2
VISO Withstand isolation voltage 3000 VRMS
× VISO , t = 1 s (100% production)

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) ISO1500 is suitable for safe electrical insulation within the safety ratings. Compliance with the safety ratings shall be ensured by means
of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.

6 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

6.7 Safety-Related Certifications

VDE CSA UL CQC TUV
Certified according to EN
Recognized under UL 61010-1:2010/A1:2019,
Certified according to DIN Certified according to IEC Certified according to
1577 Component EN 60950-
VDE V 0884-11:2017- 01 60950-1, IEC 62368-1 GB4943.1-2011
Recognition Program 1:2006/A2:2013 and EN
62368-1:2014
Maximum transient
isolation voltage, CSA 60950-1-07+A1+A2, EN 61010-
IEC 60950-1 2nd 1:2010/A1:2019,
4242 VPK;
Ed.+A1+A2, CSA 62368- Basic insulation, Altitude ≤ 300 VRMS basic isolation
Maximum repetitive peak
1-14, and IEC 62368-1 Single protection, 5000 m, Tropical Climate, ----------------
isolation voltage,
2nd Ed., for pollution 3000 VRMS 400 VRMS maximum EN 60950-
566 VPK; degree 2, material group I: working voltage 1:2006/A2:2013 and EN
Maximum surge isolation 370 VRMS 62368-1:2014, 400 VRMS
voltage,
basic isolation
4000 VPK
Certificate number: Master contract number: Certificate number:
File number: E181974 Client ID number: 77311
40040142 220991 CQC18001199097

6.8 Safety Limiting Values

Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DBQ-16 PACKAGE
RθJA = 67.9°C/W, VI = 5.5 V, TJ = 150°C,
201
TA = 25°C, see Figure 1
RθJA = 67.9°C/W, VI = 3.6 V, TJ = 150°C,
308
TA = 25°C, see Figure 1
IS Safety input, output, or supply current mA
RθJA = 67.9°C/W, VI = 2.75 V, TJ =
403
150°C, TA = 25°C, see Figure 1
RθJA = 67.9°C/W, VI = 1.89 V, TJ =
586
150°C, TA = 25°C, see Figure 1
RθJA = 67.9°C/W, TJ = 150°C, TA = 25°C,
PS Safety input, output, or total power 1105 mW
see Figure 2
TS Maximum safety temperature 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

6.9 Electrical Characteristics: Driver

Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Open circuit voltage, unloaded bus,
1.5 4.3 VCC2 V
4.5 V ≤ VCC2 ≤ 5.5 V
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V,
Driver differential-output voltage 1.5 2.5 V
|VOD| 4.5 V < VCC2 < 5.5 V (see Figure 19)
magnitude
RL = 100 Ω (see Figure 20), RS-422 load 2 2.9 V
RL = 54 Ω (see Figure 20), RS-485 load,
1.5 2.5 V
4.5 V < VCC2 < 5.5 V
Change in differential output voltage
Δ|VOD| RL = 54 Ω or RL = 100 Ω, see Figure 20 –50 50 mV
between two states
VOC Common-mode output voltage RL = 54 Ω or RL = 100 Ω, see Figure 20 0.5 × VCC2 3 V
change in steady-state common-mode
ΔVOC(SS) RL = 54 Ω or RL = 100 Ω, see Figure 20 –50 50 mV
output voltage between two states
Peak-to-peak common-mode output
VOC(PP) RL = 54 Ω or RL = 100 Ω, see Figure 20 300 mV
voltage
VD = VCC1 or VD = VGND1, VDE = VCC1,
IOS Short-circuit output current –175 175 mA
–7 V ≤ VO ≤ 12 V, see Figure 28
Ii Input current VD and VDE = 0 V or VD and VDE = VCC1 –10 10 µA
CMTI Common-mode transient immunity VD= VCC1 or GND1, VCM = 1200V, See Figure 22 85 100 kV/µs

6.10 Electrical Characteristics: Receiver

Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max are over recommended operating conditions unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, One bus
Ii1 Bus input current –100 100 µA
input at –7 V or 12 V, other input at 0 V
–7 V ≤ Common mode voltage on bus terminals ≤ (1)
VTH+ Positive-going input threshold voltage See –100 –50 mV
12 V
Negative-going input threshold –7 V ≤ Common mode voltage on bus terminals ≤ (1)
VTH– –200 –145 See mV
voltage 12 V
–7 V ≤ Common mode voltage on bus terminals ≤
Vhys Input hysteresis (VTH+ – VTH–) 20 45 mV
12 V
VCC1=5V+/-10%, IOH = –4 mA, VID = 200 mV VCC1 – 0.4 V
VCC1=3.3V+/-10%, IOH = –2 mA, VID = 200 mV VCC1 – 0.3 V
VOH Output high voltage on the R pin
VCC1=2.5V+/-10%, 1.8V+/-5%, IOH = –1 mA, VID =
VCC1 – 0.2 V
200 mV
VCC1=5V+/-10%, IOL = 4 mA, VID = –200 mV 0.4 V
VCC1=3.3V+/-10%, IOL = 2 mA, VID = –200 mV 0.3 V
VOL Output low voltage on the R pin
VCC1=2.5V+/-10%, 1.8V+/-5%, IOL = 1 mA, VID =
0.2 V
–200 mV
Output high-impedance current on
IOZ VR = 0 V or VR = VCC1, VRE = VCC1 –1 1 µA
the R pin
Ii Input current on the RE pin VRE = 0 V or VRE = VCC1 –10 10 µA
CMTI Common-mode transient immunity VID = 1.5 V or -1.5 V, VCM= 1200 V , See Figure 22 85 100 kV/µs

(1) Under any specific conditions, VTH+ is ensured to be at least Vhys higher than VTH–.

8 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

6.11 Supply Current Characteristics: Side 1(ICC1)

Bus loaded or unloaded (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER ENABLED, RECEIVER DISABLED
Logic-side
VD = VCC1, VCC1 = 5 V ± 10% 2.6 4.4 mA
supply current
Logic-side
VD = VCC1, VCC1 = 3.3 V ± 10% 2.6 4.4 mA
supply current
Logic-side
D = 1Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10% 3.2 5.1 mA
supply current
Logic-side
D = 1Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10% 3.2 5.1 mA
supply current
DRIVER ENABLED, RECEIVER ENABLED
Logic-side
VRE = VGND1, VD = VCC1, VCC1 = 5 V ± 10% 2.6 4.4 mA
supply current
Logic-side
VRE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10% 2.6 4.4 mA
supply current
Logic-side
VRE = VGND1, D = 1Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%, CL(R) (1) = 15 pF 3.4 5.2 mA
supply current
Logic-side
VRE = VGND1, D= 1Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%, CL(R) (1) = 15 pF 3.2 5.2 mA
supply current
DRIVER DISABLED, RECEIVER ENABLED
Logic-side
V(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 5 V ± 10% 1.5 3.1 mA
supply current
Logic-side
V(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 3.3 V ± 10% 1.5 3.1 mA
supply current
Logic-side
(A-B) =1Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R) (1) = 15 pF 1.7 3.2 mA
supply current
Logic-side
(A-B) = 1Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R) (1) = 15 pF 1.7 3.2 mA
supply current
DRIVER DISABLED, RECEIVER DISABLED
Logic-side
VDE = VGND1, VD = VCC1, VCC1 = 5 V ± 10% 1.5 3.1 mA
supply current
Logic-side
VDE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10% 1.5 3.1 mA
supply current

(1) CL(R) is the load capacitance on the R pin.

6.12 Supply Current Characteristics: Side 2(ICC2)

VRE = VGND1 or VRE = VCC1 (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER ENABLED, BUS UNLOADED
Bus-side supply
VD = VCC1, VCC2 = 5 V ± 10% 2.5 4.4 mA
current
DRIVER ENABLED, BUS LOADED
Bus-side supply
VD = VCC1, RL = 54 Ω, VCC2 = 5 V ± 10% 52 70 mA
current
Bus-side supply
D =1Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10% 60 80 mA
current
DRIVER DISABLED, BUS LOADED OR UNLOADED
Bus-side supply
VD = VCC1, VCC2 = 5 V ± 10% 2.4 3.9 mA
current

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

6.13 Switching Characteristics: Driver

Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max specs over recommended operating conditions unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1Mbps DEVICE
tr, tf Differential output rise time and fall time RL = 54 Ω, CL = 50 pF, see Figure 21 210 300 ns
tPHL, tPLH Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 21 210 300 ns
PWD Pulse width distortion (1), |tPHL – tPLH| RL = 54 Ω, CL = 50 pF, see Figure 21 3 30 ns
tPHZ, tPLZ Disable time See Figure 23, and Figure 24 160 250 ns
tPZH, tPZL Enable time See Figure 23, and Figure 24 200 400 ns

(1) Also known as pulse skew.

6.14 Switching Characteristics: Receiver

Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max are over recommended operating conditions unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1Mbps DEVICE
tr, tf Differential output rise time and fall time CL = 15 pF, see Figure 25 2.4 4 ns
tPHL, tPLH Propagation delay CL = 15 pF, see Figure 25 120 180 ns
PWD Pulse width distortion (1), |tPHL – tPLH| CL = 15 pF, see Figure 25 5 20 ns
tPHZ, tPLZ Disable time See Figure 26 and Figure 27 11 30 ns
tPZH, tPZL Enable time See Figure 26 and Figure 27 7 20 ns

(1) Also known as pulse skew.

6.15 Insulation Characteristics Curves

700 1200
VCC = 1.89 V
600 VCC = 2.75 V
VCC = 3.6 V 1000
Safety Limiting Current (mA)

Safety Limiting Power (mW)

VCC = 5.5 V
500
800
400
600
300
400
200

100 200

0 0
0 50 100 150 200 0 50 100 150 200
Ambient Temperature (qC) D001
Ambient Temperature (qC) D002

Figure 1. Thermal Derating Curve for Limiting Current per Figure 2. Thermal Derating Curve for Limiting Power per
VDE VDE

10 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

6.16 Typical Characteristics

35 80
ICC1 (VCC1 = 3.3V) ICC1 (VCC1=3.3V)
30 ICC2 (VCC2 = 5V) 70 ICC2 (VCC2=5V)

60
25
Supply Current (mA)

Supply current (mA)

50
20
40
15
30
10
20

5 10

0 0
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000
Data Rate (kbps) D001
Data rate (kbps) D002
TA = 25°C DE = VCC1 RE = GND1 TA = 25°C DE = VCC1 RE = GND1
Driver load = 54 Load on R = 15 pF
Figure 3. Supply Current Vs Data Rate- No Load ohm || 50 pF

Figure 4. Supply Current Vs Data Rate- with 54 Ω || 50 pf

Load
60 4.5
ICC1 (VCC1=3.3V)
Driver Differential Output Voltage (V)

ICC2 (VCC2=5V) 4
50
3.5
Supply Current (mA)

40
3

30 2.5

2
20
1.5
10
1

0 0.5
0 100 200 300 400 500 600 700 800 900 1000 0 10 20 30 40 50 60 70 80 90 100
Data rate (kbps) D003
Driver output current (mA) D005
TA = 25°C DE = VCC1 RE = GND1 DE = VCC1 D = GND1 VCC1 = 3.3 V
Driver load = 120 Load on R = 15 pF VCC2 = 5 V TA = 25°C
ohm || 50 pF

Figure 6. Driver Differential Output Voltage Vs Driver Output

Figure 5. Supply Current Vs Data Rate - with 120 Ω || 50 pf Current
Load

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

Typical Characteristics (continued)

5 4
VOH VOD (5V, 120 :)
4.5

Driver Differential Output Voltage (V)

VOL VOD (5V, 54 :)
3.5
4
Driver Output Voltage (V)

3.5
3
3
2.5 2.5
2
2
1.5
1
1.5
0.5
0 1
0 10 20 30 40 50 60 70 80 90 100 -40 -20 0 20 40 60 80 100 120 140
Driver output current (mA) D004
Ambient temp (°C) D006
DE = VCC1 D = GND1 VCC1 = 3.3 V
VCC2 = 5 V TA = 25°C

Figure 7. Driver Output Voltage Vs Driver Output Current Figure 8. Driver Differential Output Voltage Vs Temperature

55 230
50
225
45
Driver Output Current (mA)

Driver rise/fall time (ns)

40 220
35
215
30
25
210
20
15 205

10
200
5
0 195
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -40 -20 0 20 40 60 80 100 120 140
Supply Voltage VCC2 (V) D007
Ambient Temperature (°C ) D008
TA = 25°C RL = 54 ohm DE = D = VCC1 VCC1 = 3.3 V VCC2 = 5 V

Figure 9. Driver Output Current Vs Supply Voltage (VCC2) Figure 10. Driver rise/fall time vs Temperature

12 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

Typical Characteristics (continued)

215 7
VOH (1.8V)
6 VOH (3.3V)
Driver Propoagation Delay (ns)

High Level Output Voltage (V)

210 VOH (5V)

205
4

3
200

2
195
1

190 0
-40 -20 0 20 40 60 80 100 120 140 -15 -10 -5 0
Ambient Temperature (°C ) D009
High Level Output Current (mA) D010
VCC1 = 3.3 V VCC2 = 5 V TA = 25°C

Figure 11. Driver Propagation Delay vs Temperature Figure 12. Receiver Buffer High Level Output Voltage Vs
High Level Output Current
0.9 140

0.8
135
Reveiver Propagation Delay (ns)
Low Level Output Voltage (V)

0.7
130
0.6

0.5 125

0.4 120
0.3
115
0.2
Vol (1.8V)
Vol (3.3V) 110
0.1
Vol (5V)
0 105
0 5 10 15 -40 -20 0 20 40 60 80 100 120
Low Level Output Current (mA) D013
Temperature (qC) D014
TA = 25°C VCC1 = 3.3 V VCC2 = 5 V

Figure 13. Receiver Buffer Low Level Output Voltage Vs Figure 14. Receiver Propagation Delay Vs Temperature
Low Level Output Current

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

Typical Characteristics (continued)

VCC1 = 3.3 V VCC2 = 5 V DE = VCC1 VCC1 = 3.3 V VCC2 = 5 V TA = 25°C,

TA = 25°C DE = GND1 RE = GND1

Figure 15. Driver Propagation delay Figure 16. Receiver Propagation Delay

Figure 18. VCC2 Power Up / Power down- Glitch Free

Behavior
Figure 17. VCC1 Power Up / Power down- Glitch Free
Behavior

14 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

7 Parameter Measurement Information

VCC2 375
DE = VCC1
A
B VOD RL
D = 0 or VTEST
VCC1 375 +
±
GND2

Figure 19. Driver Voltages

A RL(1) / 2
A VA 0 V or D
VOD
VCC1
RL(1) / 2
B VB B
VOC

VOC GND2
ûVOC(SS)
VOC(PP)

(1) RL = 100 Ω for RS422, RL = 54 Ω for RS-485

Figure 20. Driver Voltages

VCC1
DE = VCC1

A VOD VI 50%
D RL CL(1)
tPLH tPHL
54 ± 1% 50 pF ± 20% VOD (H)
Input B 90% 90%
Generator VI 50 0V 0V
VOD 10% 10%
VOD (L)
GND1 tr tf

(1) CL includes fixture and instrumentation capacitance.

Figure 21. Driver Switching Specifications

VCC1 VCC2
10 µF
VCC1 DE
0.1 µF 0.1 µF 10 µF
A
GND1 D +
54 VOH or VOL
B ±

GND1
R

+ CL RE
VOH or VOL 1k 15 pF(1)
± GND1 GND2

+ VCM ±

(1) Includes probe and fixture capacitance.

Figure 22. Common Mode Transient Immunity (CMTI)—Half Duplex

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

Parameter Measurement Information (continued)

A
S1
D VO VCC1
VI 50 % 50 %
DE B 0V
CL(1) RL tPZH
50 pF 110 VOH
Input 90%
Generator VI 50 50%
VO
tPHZ §0V
GND2
GND1
(1) CL includes fixture and instrumentation capacitance

Figure 23. Driver Enable and Disable Times

VCC2

RL
VCC1
A 110
50 % 50 %
D VI
S1 0V
(1) tPZL tPLZ
DE B CL VCC2
50 pF VO
50%
Input 10%
50 VOL
Generator VI
GND2

GND1

Figure 24. Driver Enable and Disable Times

3V

A 50 % 50 %
R VO VI
0V
Input B
50 1.5 V CL(1)
Generator VI tPLH tPHL
RE 15 pF VOH
90%
50% 50%
VO
10%
VOL
tr tf

(1) CL includes fixture and instrumentation capacitance.

Figure 25. Receiver Switching Specifications

VCC1
50%
VI
0V
tPZH tPHZ
VOH
90%
VO 50%
§0V
tPZL
tPLZ VCC1
VO 50%
10%
VOL

Figure 26. Receiver Enable and Disable Times

16 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

Parameter Measurement Information (continued)

VCC1 VCC1
VI 50%
A 1k 0V
0 V or 1.5 V R VO
B S1 tPZH
1.5 V or 0 V CL VOH A at 1.5 V
RE 15 pF
VO 50% B at 0 V
§ 0 V S1 to GND
Input tPZL
VI 50 A at 0 V
Generator VCC1
B at 1.5 V
VO 50%
S1 to
VOL
VCC1

Figure 27. Receiver Enable and Disable Times

A A
Steady-State Steady State
G G ±7 9 ” 9 ” 12 V
Logic Input Logic Input I(1)
(1 or 0) (1 or 0)
B B V
C C

GND GND

(1) The driver should not sustain any damage with this configuration.

Figure 28. Short-Circuit Current Limiting

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

8 Detailed Description

8.1 Overview
The ISO1500 device is an isolated RS-485/RS-422 transceiver designed to operate in harsh industrial
environments. This device supports data transmissions up to 1 Mbps. The ISO1500 device has a 3-channel
digital isolator and an RS-485 transceiver in an ultra-small SSOP package. The silicon-dioxide based capacitive
isolation barrier supports an isolation withstand voltage of 3 kVRMS and an isolation working voltage of 566 VPK.
Isolation breaks the ground loop between the communicating nodes and lets data transfer in the presence of
large ground potential differences. The wide logic supply of the device (VCC1) supports interfacing with 1.8-V, 2.5-
V, 3.3-V. and 5-V control logic. Functional Block Diagram shows the functional block diagram of the the half-
duplex device.

8.2 Functional Block Diagram

VCC2
VCC1 VCC2
VCC
DE Tx Rx

D Tx Rx D A
Half duplex
Rx Tx B
R R

RE
GND1 GND2 GND2

8.3 Feature Description

Table 1 shows an overview of the device features.

Table 1. Device Features

PART NUMBER ISOLATION DUPLEX DATA RATE PACKAGE
ISO1500 Basic Half 1 Mbps 16-pin SSOP

8.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO1500
device has dedicated circuitry to help protect the transceiver from Contact ESD per IEC61000-4-2.

8.3.2 Failsafe Receiver

The differential receiver of the ISO1500 device has failsafe protection from invalid bus states caused by:
• Open bus conditions such as a broken cable or a disconnected connector
• Shorted bus conditions such as insulation breakdown of a cable that shorts the twisted-pair
• Idle bus conditions that occur when no driver on the bus is actively driving
The differential input of the RS-485 receiver is 0 in any of these conditions for a terminated transmission line.
The receiver outputs a failsafe logic-high state so that the output of the receiver is not indeterminate.

18 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

The receiver thresholds are offset in the receiver failsafe protection so that the indeterminate range of the input
does not include a 0 V differential. The receiver output must generate a logic high when the differential input (VID)
is greater than 200 mV to comply with the RS-485 standard. The receiver output must also generate a output a
logic low when VID is less than –200 mV to comply with the RS-485 standard. The receiver parameters that
determine the failsafe performance are VTH+, VTH–, and VHYS. Differential signals less than –200 mV always
cause a low receiver output as shown in the Electrical Characteristics table. Differential signals greater than 200
mV always cause a high receiver output. A differential input signal that is near zero is still greater than the VTH+
threshold which makes the receiver output logic high. The receiver output goes to a low state only when the
differential input decreases by VHYS to less than VTH+.
The internal failsafe biasing feature removes the need for the two external resistors that are typically required
with traditional isolated RS-485 transceivers as shown in Figure 29.
Traditional ISO1500
transceiver (R1 and R2 not needed)

VCC2 VCC2
VCC1 VCC2 VCC1 VCC2

R1

A A

RT RS-485 RT RS-485
Bus Bus
B B

R2

GND1 GND2 GND1 GND2

ISO ISO
Galvanic Ground Ground
Galvanic
Isolation Barrier Isolation Barrier

Figure 29. Failsafe Transceiver

8.3.3 Thermal Shutdown

The ISO1500 device has a thermal shutdown circuit to protect against damage when a fault condition occurs. A
driver output short circuit or bus contention condition can cause the driver current to increase significantly which
increases the power dissipation inside the device. An increase in the die temperature is monitored and the device
is disabled when the die temperature becomes 170℃ (typical) which lets the device decrease the temperature.
The device is enabled when the junction temperature becomes 163℃ (typical).

8.3.4 Glitch-Free Power Up and Power Down

Communication on the bus that already exist between a master node and slave node in an RS485 network must
not be disturbed when a new node is swapped in or out of the network. No glitches on the bus occur when the
device is:
• Hot plugged into the network in an unpowered state
• Hot plugged into the network in a powered state and disabled state
• Powered up or powered down in a disabled state when already connected to the bus
The ISO1500 device does not cause any false data toggling on the bus when powered up or powered down in a
disabled state with supply ramp rates from 100 µs to 10 ms.

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

8.4 Device Functional Modes

Table 2 shows the driver functional modes.

Table 2. Driver Functional Table (1)

DRIVER ENABLE OUTPUTS
VCC1 VCC2 INPUT D
DE A B
H H H L
L H L H
PU PU X L Hi-Z Hi-Z
X Open Hi-Z Hi-Z
Open H H L
PD (2) PU X X Hi-Z Hi-Z
X PD X X Hi-Z Hi-Z

(1) PU = Powered Up; PD = Powered Down; H = High Level; L = Low level; X = Irrelevant, Hi-Z = High impedance state
(2) A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined
output.

When the driver enable pin, DE, is logic high, the differential outputs, A and B, follow the logic states at data
input, D. A logic high at the D input causes the A output to go high and the B output to go low. Therefore the
differential output voltage defined by Equation 1 is positive.
VOD = VA – VB (1)
A logic low at the D input causes the B output to go high and the A output to go low. Therefore the differential
output voltage defined by Equation 1 is negative. A logic low at the DE input causes both outputs to go to the
high-impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin
has an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when
the DE pin is left open. The D pin has an internal pullup resistor. The A output goes high and the B output goes
low when the D pin is left open while the driver enabled.
Table 3 shows the receiver functional modes.

Table 3. Receiver Functional Table (1)

VCC1 VCC2 DIFFERENTIAL INPUT RECEIVER ENABLE RE OUTPUT R
VID = VA – VB
–0.02 V ≤ VID L H
–0.2 V < VID < 0.02 V L Indeterminate
VID≤ –0.2 V L L
PU PU
X H Hi-Z
X Open Hi-Z
Open, Short, Idle L H
PD (2) PU X X Hi-Z
PU PD X L H
PD (2) PD X X Hi-Z

(1) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state
(2) A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined
output.

20 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when
the differential input voltage defined by Equation 2 is greater than the positive input threshold, VTH+.
VID = VA – VB (2)
The receiver output, R, goes low when the differential input voltage defined by Equation 2 is less than the
negative input threshold, VTH–. If the VID voltage is between the VTH+ and VTH– thresholds, the output is
indeterminate. The receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when
the RE pin is logic high or left open. The internal biasing of the receiver inputs causes the output to go to a
failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one
another (short-circuit), or the bus is not actively driven (idle bus).

8.4.1 Device I/O Schematics

D and RE Inputs DE Input

VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1

1.5 M

985 985
Input Input

1.5 M

R Output

VCC1

~20
R

Figure 30. Device I/O Schematics

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ISO1500 device is designed for bidirectional data transfer on multipoint RS-485 networks. The design of
each RS-485 node in the network requires an ISO1500 device and an isolated power supply as shown in
Figure 32.
An RS-485 bus has multiple transceivers that connect in parallel to a bus cable. Both cable ends are terminated
with a termination resistor, RT, to remove line reflections. The value of RT matches the characteristic impedance,
Z0, of the cable. This method, known as parallel termination, lets higher data rates be used over a longer cable
length.
In half-duplex implementation, as shown in Figure 31, the driver and receiver enable pins let any node at any
given moment be configured in either transmit or receive mode which decreases cable requirements.

Integrated isolation barrier allows for communication between

nodes with large ground potential differences

R R
A A
RE RE
ISO1500 RT RT ISO1500
DE B B DE
D
D
A B A B
ISO1500
ISO1500
R
RE
DE
D

R
RE
DE
D

Figure 31. Half-Duplex Network Circuit

22 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

9.2 Typical Application

Figure 32 shows the application circuit of the ISO1500 device.

4 8 1 5
GND D2 IN OUT
3
SN6505 3 7 EN
3.3 V TPS76350
EN VCC 2 6
2 4
GND NC
1 5
CLK D1

1 10, 16
VCC1 VCC2
0.1 …F 2 0.1 …F × 2
VDD GND1

3
GPIO1 R NC 14

MCU 4 13
RE B
GPIO2 5 ISO1500
12
DE A
L1 3.3V 6 NC 11
GPIO3 D Optional bus
DGND protection
N PSU
7 NC

PE 0V 8 9,15
GND1 GND2

Galvanic
Protective Chasis Digital ISO
Isolation Barrier
Earth Ground Ground Ground

Figure 32. Typical Application

9.2.1 Design Requirements

Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISO1500 device only requires external bypass capacitors to operate.

9.2.2 Detailed Design Procedure

The RS-485 bus is a robust electrical interface suitable for long-distance communications. The RS-485 interface
can be used in a wide range of applications with varying requirements of distance of communication, data rate,
and number of nodes.

9.2.2.1 Data Rate and Bus Length

The RS-485 standard has typical curves similar to those shown in Figure 33. These curves show the inverse
relationship between signaling rate and cable length. If the data rate of the payload between two nodes is lower,
the cable length between the nodes can be longer.

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

Typical Application (continued)

10000
5%, 10%, and 20% Jitter

Cable Length (ft)

1000
Conservative
Characteristics

100

10
100 1k 10 k 100 k 1M 10 M 100 M
Data Rate (bps)

Figure 33. Cable Length vs Data Rate Characteristics

Applications can increase the cable length at slower data rates compared to what is shown in Figure 33 by
allowing for jitter of 5% or higher. Use Figure 33 as a guideline for cable selection, data rate, cable length and
subsequent jitter budgeting.

9.2.2.2 Stub Length

In an RS-485 network, the distance between the transceiver inputs and the cable trunk is known as the stub. The
stub should be as short as possible when a node is connected to the bus. Stubs are a non-terminated piece of
bus line that can introduce reflections of varying phase as the length of the stub increases. The electrical length,
or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver as a general guideline.
Therefore, the maximum physical stub length (L(STUB)) is calculated as shown in Equation 3.
L(STUB) ≤ 0.1 × tr × v × c
where
• tr is the 10/90 rise time of the driver.
• c is the speed of light (3 × 108 m/s).
• v is the signal velocity of the cable or trace as a factor of c. (3)

9.2.2.3 Bus Loading

The current supplied by the driver must supply into a load because the output of the driver depends on this
current. Add transceivers to the bus to increase the total bus loading. The RS-485 standard specifies a
hypothetical term of a unit load (UL) to estimate the maximum number of possible bus loads. The UL represents
a load impedance of approximately 12 kΩ. Standard-compliant drivers must be able to drive 32 of these ULs.
The ISO1500 device has 1/8 UL impedance transceiver and can connect up to 256 nodes to the bus.

10 Power Supply Recommendations

To make sure device operation is reliable at all data rates and supply voltages, a 0.1-μF bypass capacitor is
recommended at the logic and transceiver supply pins (VCC1 and VCC2). The capacitors should be placed as near
to the supply pins as possible. Side 2 requires one VCC2 decoupling capacitor on each VCC2 pin. If only one
primary-side power supply is available in an application, isolated power can be generated for the secondary-side
with the help of a transformer driver such as TI's SN6505B device. For such applications, detailed power supply
design and transformer selection recommendations are available in the SN6505 Low-Noise 1-A Transformer
Drivers for Isolated Power Supplies data sheet.

24 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

11 Layout

11.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 34). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
Figure 35 shows the recommended placement and routing of the device bypass capacitors and optional TVS
diodes. Put the two VCC2 bypass capacitors on the top layer and as near to the device pins as possible. Do not
use vias to complete the connection to the VCC2 and GND2 pins. If an additional supply voltage plane or signal
layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the
stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system
can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.
Refer to the Digital Isolator Design Guide for detailed layout recommendations.

11.1.1 PCB Material

For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.

11.2 Layout Example

High-speed traces
10 mils

Ground plane

Keep this space FR-4

40 mils free from planes, 0r ~ 4.5
traces, pads, and
vias

Power plane
10 mils

Low-speed traces

Figure 34. Recommended Layer Stack

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: ISO1500
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020 www.ti.com

Layout Example (continued)

Minimize
distance to
supply pins
VCC1 VCC2

VCC1 VCC2 Optional bus

0.1 µF C C 0.1 µF
GND1 GND2
protection

Isolation Capacitor
R NC
MCU RE B
D1 RS-485

R
x

DE A
D NC
NC VCC2
C 0.1 µF
GND1 GND2

GND1 GND2
Plane Plane

Figure 35. Layout Example

26 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: ISO1500

 ISO1500
www.ti.com SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, ISO1500 Isolated RS-485 Half-Duplex Evaluation Module use's guide

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resource

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: ISO1500
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

ISO1500DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 1500
& no Sb/Br)
ISO1500DBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 1500
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Feb-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Feb-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO1500DBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Feb-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO1500DBQR SSOP DBQ 16 2500 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBQ0016A SCALE 2.800
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP
[5.80-6.19] .004 [0.1] C
A PIN 1 ID AREA
14X .0250
[0.635]
16
1

2X
.189-.197
[4.81-5.00] .175
NOTE 3 [4.45]

8
9
16X .008-.012
B .150-.157 [0.21-0.30] .069 MAX
[3.81-3.98] [1.75]
NOTE 4 .007 [0.17] C A B

.005-.010 TYP
[0.13-0.25]

SEE DETAIL A

.010
[0.25]
GAGE PLANE

.004-.010
0 -8 [0.11-0.25]
.016-.035
[0.41-0.88] DETAIL A
(.041 ) TYPICAL
[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6] SEE
SYMM
DETAILS
1
16

16X (.016 )
[0.41]

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING

.002 MAX .002 MIN

[0.05] [0.05]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6]
SYMM
1
16

16X (.016 )
[0.41]
SYMM

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated